ESMT
Mobile DDR SDRAM
Features
JEDEC Standard
Internal pipelined double-data-rate architecture, two data
access per clock cycle
Bi-directional data strobe (DQS)
No DLL; CLK to DQS is not synchronized.
Differential clock inputs (CLK and CLK )
Four bank operation
CAS Latency : 2, 3
Burst Type : Sequential and Interleave
Burst Length : 2, 4, 8, 16
Special function support
-
PASR (Partial Array Self Refresh)
-
Internal TCSR (Temperature Compensated Self
Refresh)
-
DS (Drive Strength)
M53S64322A (2E)
512K x 32 Bit x 4 Banks
Mobile
DDR SDRAM
All inputs except data & DM are sampled at the rising
edge of the system clock(CLK)
DQS is edge-aligned with data for READ; center-aligned
with data for WRITE
Data mask (DM) for write masking only
V
DD
/V
DDQ
= 2.5V ± 0.2V
Auto & Self refresh
15.6us refresh interval (64ms refresh period, 4K cycle)
LVCMOS-compatible inputs
Ordering Information
Product ID
M53S64322A -5BG2E
M53S64322A -6BG2E
M53S64322A -7.5BG2E
Max Freq.
200MHz
166MHz
133MHz
2.5V
144 ball FBGA
Pb-free
V
DD
Package
Comments
Functional Block Diagram
CLK
CLK
CKE
Address
Mode Register &
Extended Mode
Register
Clock
Generator
Bank D
Bank C
Bank B
Row Decoder
Row
Address
Buffer
&
Refresh
Counter
Bank A
DQS
Sense Amplifier
DM
CAS
WE
Data Control Circuit
Input & Output
Buffer
Latch Circuit
RAS
Control Logic
CS
Command Decoder
Column
Address
Buffer
&
Refresh
Counter
Column Decoder
DQ
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2013
Revision : 1.0
1/47
ESMT
BALL CONFIGURATION (TOP VIEW)
M53S64322A (2E)
(BGA144, 12mmX12mmX1.4m Body, 0.8mm Ball Pitch)
2
B
C
D
E
F
G
H
J
K
L
M
N
DQS0
DQ4
DQ6
DQ7
DQ17
DQ19
DQS2
DQ21
DQ22
CAS
RAS
CS
3
DM0
VDDQ
DQ5
VDDQ
DQ16
DQ18
DM2
DQ20
DQ23
WE
NC
NC
4
VSSQ
NC
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
NC
BA0
5
DQ3
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
BA1
A0
6
DQ2
DQ1
VSSQ
VSSQ
VSS
Thermal
7
DQ0
VDDQ
VDD
VSS
VSS
Thermal
8
DQ31
VDDQ
VDD
VSS
VSS
Thermal
9
DQ29
DQ30
VSSQ
VSSQ
VSS
Thermal
10
DQ28
VDDQ
VSSQ
VSS
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
NC
A7
11
VSSQ
NC
VSSQ
VDD
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDD
CLK
A8
12
DM3
VDDQ
DQ26
VDDQ
DQ15
DQ13
DM1
DQ11
DQ9
NC
CLK
CKE
13
DQS3
DQ27
DQ25
DQ24
DQ14
DQ12
DQS1
DQ10
DQ8
NC
NC
NC
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
Thermal
VSS
A10/AP
A2
A1
VSS
VDD
NC
A3
VSS
VDD
A9
A4
VSS
NC
A5
A6
Ball Description
Ball Name
Function
Address inputs
- Row address A0~A10
- Column address A0~ A7
A10/AP : AUTO Precharge
BA0~BA1 : Bank selects (4 Banks)
Data-in/Data-out
Row address strobe
Column address strobe
Write enable
Ground
Power
Bi-directional Data Strobe. DQS0
corresponds to the data on DQ0~DQ7;
DQS1 correspond to the data on
DQ8~DQ15; DQS2 correspond to the data
on DQ16~DQ23; DQS3 correspond to the
data on DQ24~DQ31.
Ball Name
Function
DM is an input mask signal for write data.
DM0 corresponds to the data on
DQ0~DQ7; DM1 correspond to the data on
DQ8~DQ15; DM2 correspond to the data
on DQ16~DQ23; DM3 correspond to the
data on DQ24~DQ31.
Clock input
Clock enable
Chip select
Supply Voltage for DQ
Ground for DQ
No connection
A0~A10,
BA0~BA1
DM0~DM3
DQ0~DQ31
RAS
CAS
WE
CLK, CLK
CKE
CS
V
DDQ
V
SSQ
NC
V
SS
V
DD
DQS0~DQS3
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2013
Revision : 1.0
2/47
ESMT
Absolute Maximum Rating
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Voltage on V
DDQ
supply relative to V
SS
Operating ambient temperature
Storage temperature
Power dissipation
Short circuit current
Note:
Symbol
V
IN
, V
OUT
V
DD
V
DDQ
T
A
T
STG
P
D
I
OS
M53S64322A (2E)
Value
-0.5 ~ 3.6
-0.5 ~ 3.6
-0.5 ~ 3.6
0 ~ +70
-55 ~ +150
1.0
50
Unit
V
V
V
°C
°C
W
mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operation Condition & Specifications
DC Operation Condition
Recommended operating conditions (Voltage reference to V
SS
= 0V)
Parameter
Supply voltage
I/O Supply voltage
Input logic high voltage (for Address and Command)
Input logic low voltage (for Address and Command)
Input logic high voltage (for DQ, DM, DQS)
Input logic low voltage (for DQ, DM, DQS)
Output logic high voltage
Output logic low voltage
Input Voltage Level, CLK and CLK inputs
Input Differential Voltage, CLK and CLK inputs
Input leakage current
Output leakage current
Note:
1. V
ID
is the magnitude of the difference between the input level on CLK and the input level on CLK .
Symbol
V
DD
V
DDQ
V
IH
(DC)
V
IL
(DC)
V
IHD
(DC)
V
ILD
(DC)
V
OH
(DC)
V
OL
(DC)
V
IN
(DC)
V
ID
(DC)
I
I
I
OZ
Min
2.3
2.3
0.8 x V
DDQ
-0.3
0.7 x V
DDQ
-0.3
0.9 x V
DDQ
-
-0.3
0.4 x V
DDQ
-2
-5
Max
2.7
2.7
V
DDQ
+ 0.3
0.2 x V
DDQ
V
DDQ
+ 0.3
0.3 x V
DDQ
-
0.1 x V
DDQ
V
DDQ
+ 0.3
V
DDQ
+ 0.6
2
5
Unit
V
V
V
V
V
V
V
V
V
V
μA
μA
1
I
OH
= -0.1mA
I
OL
= 0.1mA
Note
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2013
Revision : 1.0
3/47
ESMT
DC Characteristics
Recommended operating condition (Voltage reference to V
SS
= 0V)
Parameter
Operating Current
(One Bank Active)
Symbol
Test Condition
t
RC
= t
RC
(min); t
CK
= t
CK
(min); CKE = HIGH;
I
DD0
CS = HIGH between valid commands; address inputs
are SWITCHING; data input signals are STABLE
All banks idle, CKE = LOW; CS = HIGH, t
CK
= t
CK
(min); address & control inputs are SWITCHING; data
input signals are STABLE
All banks idle, CKE = LOW; CS = HIGH, CLK = LOW,
I
DD2PS
CLK = HIGH; address & control inputs are
SWITCHING; data input signals are STABLE
All banks idle, CKE = HIGH; CS = HIGH, t
CK
= t
CK
(min); address & control inputs are SWITCHING; data
input signals are STABLE
All banks idle, CKE = HIGH; CS = HIGH, CLK = LOW,
I
DD2NS
CLK = HIGH; address & control inputs are
SWITCHING; data input signals are STABLE
One bank active, CKE = LOW; CS = HIGH,
t
CK
= t
CK
(min); address & control inputs are
SWITCHING; data input signals are STABLE
One bank active, CKE = LOW; CS = HIGH,
I
DD3PS
CLK = LOW, CLK = HIGH; address & control inputs
are SWITCHING; data input signals are STABLE
One bank active, CKE = HIGH, CS = HIGH,
t
CK
= t
CK
(min); address & control inputs are
SWITCHING; data input signals are STABLE
One bank active, CKE = HIGH; CS = HIGH,
I
DD3NS
CLK= LOW, CLK = HIGH; address & control inputs
are SWITCHING; data input signals are STABLE
One bank active; BL=4; CL=3; t
CK
= t
CK
(min);
continuous read bursts; I
OUT
= 0 mA; address inputs are
SWITCHING; 50% data changing each burst
One bank active; BL=4; t
CK
= t
CK
(min); continuous
write bursts; I
OUT
= 0 mA; address inputs are
SWITCHING; 50% data changing each burst
Burst refresh; t
CK
= t
CK
(min);
CKE = HIGH; address inputs are
SWITCHING; data input signals are
I
DD5A
STABLE
t
RFC
= t
REFI
t
RFC
= t
RFC
(min)
M53S64322A (2E)
Version
-5
55
-6
50
-7.5
45
Unit
mA
Precharge Standby
Current in
power-down
mode
I
DD2P
900
μA
900
μA
I
DD2N
Precharge Standby
Current in non
power-down mode
10
9
8
mA
10
9
8
mA
I
DD3P
Active Standby
Current
in power-down
mode
3
mA
1.2
mA
Active Standby
Current
in non power-down
mode
(One Bank Active)
I
DD3N
30
27
25
mA
7
6
5
mA
I
DD4R
Operating Current
(Burst Mode)
120
110
100
mA
I
DD4W
100
90
80
mA
I
DD5
Auto Refresh
Current
70
60
50
mA
10
8
6
mA
Elite Semiconductor Memory Technology Inc.
Publication Date : Jan. 2013
Revision : 1.0
4/47
ESMT
TCSR range
CKE = LOW, CLK = LOW,
Self Refresh Current
I
DD6
CLK = HIGH; EMRS set to all
0’s; address & control & data bus
inputs are STABLE
Full array
1/2 array
1/4 array
1/8 array
Deep Power Down
Current
I
DD8
address & control & data inputs are STABLE
M53S64322A (2E)
45
950
900
850
800
10
85
1000
950
900
850
°C
μA
μA
μA
μA
μA
Note: 1. Input slew rate is 1V/ns.
2. I
DD
specifications are tested after the device is properly initialized.
3. Definitions for I
DD
: LOW is defined as V
IN
≤
0.1 * V
DDQ
;
HIGH is defined as V
IN
≥
0.9 * V
DDQ
;
STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once
per two clock cycles;
- data bus inputs: DQ changing between HIGH and LOW once per clock
cycle; DM and DQS are STABLE.
AC Operation Conditions & Timing Specification
AC Operation Conditions
Parameter
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
Input Differential Voltage, CLK and CLK inputs
Input Crossing Point Voltage, CLK and CLK inputs
Symbol
V
IHD
(AC)
V
ILD
(AC)
V
ID
(AC)
V
IX
(AC)
Min
0.8 x V
DDQ
-0.3
0.6 x V
DDQ
0.4 x V
DDQ
Max
V
DDQ
+0.3
0.2 x V
DDQ
V
DDQ
+0.6
0.6 x V
DDQ
Unit
V
V
V
V
1
2
Note
Note: 1. V
ID
is the magnitude of the difference between the input level on CLK and the input on CLK .
2. The value of V
IX
is expected to equal 0.5*V
DDQ
of the transmitting device and must track variations in the DC level of the
same.
Input / Output Capacitance
(V
DD
= 2.5V, V
DDQ
= 2.5V, T
A
= 25 °C , f = 1MHz)
Parameter
Input capacitance
(A0~A10, BA0~BA1, CKE, CS , RAS , CAS ,
WE
)
Input capacitance (CLK, CLK )
Data & DQS input/output capacitance
Input capacitance (DM)
Elite Semiconductor Memory Technology Inc.
Symbol
C
IN1
C
IN2
C
OUT
C
IN3
Min
1.5
1.5
3.0
3.0
Max
3.0
3.0
5.0
5.0
Unit
pF
pF
pF
pF
Publication Date : Jan. 2013
Revision : 1.0
5/47
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