IDTQS74FCT2373T/AT
HIGH-SPEED CMOS BUS INTERFACE 8-BIT LATCH
INDUSTRIAL TEMPERATURE RANGE
HIGH-SPEED CMOS
BUS INTERFACE
8-BIT LATCH
FEATURES:
−
−
−
−
−
−
−
−
−
CMOS power levels: <7.5mW static
Undershoot clamp diodes on all inputs
True TTL input and output compatibility
Ground bounce controlled outputs
Reduced output swing of 0 to 3.5V
Built-in 25Ω series resistor outputs reduce reflection and other
system noise
Std. and A speed grades
I
OL
= 12mA
Available in SOIC and QSOP packages
IDTQS74FCT2373T/AT
DESCRIPTION:
The IDTQS74FCT2373T is an 8-bit high-speed CMOS TTL-compatible
buffered latch, with three-state outputs that have 25Ω resistors at the output.
This device is useful for driving transmission lines and reducing system
noise. The 2373 series parts can replace the 373 series to reduce noise
in existing designs. All inputs have clamp diodes for undershoot noise
suppression. All outputs have ground bounce suppression. Outputs will
not load an active bus when Vcc is removed from the device.
FUNCTIONAL BLOCK DIAGRAM
25
Ω
Dx
LE
OE
11
1
D
LE
Q
Ox
INDUSTRIAL TEMPERATURE RANGE
1
c
2001 Integrated Device Technology, Inc.
JANUARY 2001
DSC-5406/2
IDTQS74FCT2373T/AT
HIGH-SPEED CMOS BUS INTERFACE 8-BIT LATCH
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
2
3
4
5
6
7
8
9
10
SOIC/ QSOP
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
20
19
18
17
V
CC
O
7
D
7
D
6
O
6
O
5
D
5
D
4
O
4
LE
Symbol
V
TERM
T
STG
I
OUT
I
IK
I
OK
Description
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current Max Sink Current/Pin
Input Diode Current, V
IN
< 0
Output Diode Current, V
OUT
< 0
(1)
Unit
V
°C
mA
mA
mA
FCTL
Max.
– 0.5 to +7
– 65 to +150
120
– 20
– 50
SO20-2
SO20-8
16
15
14
13
12
11
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
4
8
Max.
—
—
Unit
pF
pF
FCT_2
NOTE:
1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
Dx
Ox
LE
OE
I/O
I
O
I
I
Description
Data Inputs
Data Outputs (3-State)
Latch Enable Input (Active HIGH)
Output Enable Input (Active LOW)
(1)
Outputs
Q
x
Z
H
L
L
H
Q
Function
Disable Outputs
Enable Outputs
Pass Inputs
Hold Prior Data
FUNCTION TABLE
Inputs
OE
H
L
L
L
L
L
LE
X
L
L
H
H
L
D
X
X
X
X
L
H
X
Internal
Q Value
X
H
L
L
H
Q
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
Q = Output level before the indicated steady-state input conditions
were established.
2
IDTQS74FCT2373T/AT
HIGH-SPEED CMOS BUS INTERFACE 8-BIT LATCH
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 5%
Symbol
V
IH
V
IL
∆V
T
I
IH
I
IL
I
OZ
I
OR
V
IC
V
OH
V
OL
R
OUT
Parameter
Input HIGH Level
Input LOW Level
Input Hysteresis
Input HIGH Current
Input LOW Current
Off-State Output Current (Hi-Z)
Current Drive
Input Clamp Voltage
Output HIGH Voltage
Output LOW Voltage
Output Resistance
V
CC
= Max.
V
CC
= Min., V
OUT
= 2.0V
(2)
V
CC
= Min., I
IN
= –18mA, T
A
= 25
°
C
(2)
V
CC
= Min.
V
CC
= Min.
V
CC
= Min.
I
OH
= -15mA
I
OL
= 12mA
I
OL
= 12mA
0
≤
V
IN
≤
Vcc
—
50
—
2.4
—
20
—
—
–0.7
—
—
28
±5
—
–1.2
—
0.5
40
µA
mA
V
V
V
Ω
Test Conditions
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
TLH
- V
THL
for all inputs
V
CC
= Max.
0
≤
V
IN
< Vcc
Min.
2
—
—
—
Typ.
(1)
—
—
0.2
—
Max.
—
0.8
—
±5
Unit
V
V
V
µA
NOTES:
1. Typical values are at V
CC
= 5.0V, T
A
= 25°C.
2. This parameter is guaranteed but not tested.
POWER SUPPLY CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 5%
Symbol
I
CC
Parameter
Quiescent Power Supply Current
Test Conditions
(1)
V
CC
= Max.
freq = 0
0V
≤
V
IN
≤
0.2V or
Vcc-0.2V
≤
V
IN
≤
Vcc
V
CC
= Max.
V
IN
= 3.4V
(2)
freq = 0
V
CC
= Max.
Outputs Open and Enabled
One Bit Toggling
50% Duty Cycle
Other inputs at GND or Vcc
(3,4)
Min.
—
Max.
1.5
Unit
mA
∆I
CC
Supply Current per Input TTL Inputs HIGH
—
2
mA
I
CCD
Supply Current per Input per MHz
—
0.25
mA/MHz
FCTL
NOTES:
1. For conditions shown as Min. or Max., use the appropriate values specified under DC Electrical Characteristics.
2. Per TLL driven input (V
IN
= 3.4V).
3. For flip-flops, I
CCD
is measured by switching one of the data input pins so that the output changes every clock cycle. This is a measurement of
device power consumption only and does not include power to drive load capacitance or tester capacitance.
4. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Output Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
3
IDTQS74FCT2373T/AT
HIGH-SPEED CMOS BUS INTERFACE 8-BIT LATCH
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
(1)
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= -40°C to +85°C, V
CC
= 5.0V ± 5%
74FCT2373T
Symbol
t
PHL
t
PLH
t
PHL
t
PLH
t
PZH
t
PZL
t
PHZ
t
PLZ
t
S
t
H
t
W
Parameter
(2)
Propagation Delay
Data to Ox
Propagation Delay
LE to Ox
Output Enable Time
OE
to Yx
Output Disable Time
(3)
OE
to Yx
Data Setup Time
Data hold Time
LE Pulse Width HIGH
(3)
Min.
1.5
2
1.5
1.5
2
1.5
6
Max.
8
13
11
7
—
—
—
Min.
1.5
2
1.5
1.5
2
1.5
5
74FCT2373AT
Max.
5.2
8.5
6.5
5.5
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. C
LOAD
= 50pF, R
LOAD
= 500Ω unless otherwise noted.
2. Minimums guaranteed but not tested.
3. This parameter is guaranteed by design but not tested.
4
IDTQS74FCT2373T/AT
HIGH-SPEED CMOS BUS INTERFACE 8-BIT LATCH
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CIRCUITS FOR ALL OUTPUTS
V
CC
500
Ω
V
IN
Pulse
Generator
D.U.T.
50pF
R
T
C
L
500
Ω
V
OUT
7.0V
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
All Other Tests
Open
FCTL
Switch
Closed
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
FC TL lin k
SET-UP, HOLD, AND RELEASE TIMES
DATA
INPUT
t
SU
TIM ING
INPUT
ASYNCHRONOUS C ONTROL
PRES ET
CLEAR
ETC.
SYNCHRO NOUS CONTRO L
PRES ET
CLEAR
CLOCK ENABLE
ETC.
t
REM
t
H
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
FC TL lin k
PULSE WIDTH
LO W -HIGH-LOW
PULSE
t
W
HIGH-LOW -HIGH
PULSE
FC TL lin k
1.5V
1.5V
t
SU
t
H
PROPAGATION DELAY
SAM E PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE P HASE
INPUT TRANSITION
t
PH L
t
PH L
3V
1.5V
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
FC TL lin k
ENABLE AND DISABLE TIMES
ENAB LE
DISA BLE
3V
CO NTROL
INPUT
t
PZL
OUTPUT
NO RM A LLY
LO W
SW ITCH
CLOSE D
t
PZH
OUTPUT
NO RM A LLY
HIGH
SW ITCH
OPEN
3.5V
1.5V
0.3V
t
PHZ
0.3V
1.5V
0V
0V
FC TL lin k
1.5V
t
PLZ
0V
3.5V
V
OL
V
OH
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-
HIGH
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns
5
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