AN5177 Application Note
AN5177
Improved Gate Drive For GTO Series Connections
Application Note
Replaces September 2000 version, AN5177-3.0
AN5177-3.1 July 2002
Using an improved gate drive to ease GTO series connection
problems.
INTRODUCTION
There are problems encountered with dynamic voltage sharing
of series connected GTOs both at turn-on and turn-off. This
application note will deal with the problems associated with turn-
off and a further note will address turn-on problems.
Switching high voltages using rectifier diodes or thyristors is
routinely done using devices connected in series. With resistor
and capacitor networks connected, 100 devices or more can be
wired in series.
The basic problem of series connection is to ensure good voltage
sharing between devices under both static and dynamic
conditions. By using devices selected within defined limits of
leakage current and reverse recovery charge, together with
correctly sized resistors and capacitors reliable operation is
assured.
Unfortunately, series connection of GTOs involves more
restraints. For traditional applications such as rail traction where
high turn-off currents are important series connection of GTOs
has not usually been cost effective. A higher voltage GTO has
been the preferred solution. However, this application note
shows that even standard design GTOs when used with improved
performance gate drive units can be successfully connected in
series for certain applications.
In this note, a specific type of application is considered where
reverse blocking GTOs are used in series in a current source
inverter. In this application, the GTOs are not usually required to
turn-off near to their I
TCM
limits.
Fig. 1 GTOs in series with snubber networks
voltage source inverters turn-off by anode current reversal is not
usually relevant.
THE SERIES CONNECTION PROBLEM
Three modes of operation need to be considered:
1. At GTO turn-on.
2. At GTO turn-off by gate commutation. This is the conventional
mode for most GTO applications.
3. At GTO turn-off by anode current reversal i.e. natural
commutation. This is similar to diode reverse recovery.
All these operating modes apply to current source inverters. For
TURN-ON
Figure 1 shows two GTOs in series with snubber networks fitted.
For simplicity, static sharing parallel resistors are not shown.
There will always be a time difference,
∆T,
between the GTOs
turning on. This time difference is the combination of differences
in td and tr of the GTOs, together with the gate drive units
propagation time variations.
Figure 2 shows the waveforms at turn-on.
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AN5177 Application Note
∆
t
gs
This is the difference in storage time between the GTOs in
series. Traditionally, GTOs are turned off slowly, typically with
dIg/dt = -40A/µs. With this condition,
∆t
gs
values are fairly large.
The gate drive unit described achieves turn off current rates of
250A/µs so that tgs and
∆t
gs
are much smaller.
Cs
Snubber capacitor values need to be high to reduce the effect of
high
∆t
gs
. It follows that if
∆t
gs
can be reduced so can Cs.
TURN-OFF BY CURRENT REVERSAL
This is the reverse recovery mode, as with a diode and
conventional thyristors and is only applicable to reverse blocking
GTOs. In this recovery mode the gate drive unit has no effect.
Fig. 2 Turn-on waveforms
Sharing considerations are as for fast recovery diodes. Thus, to
minimise the value of the snubber capacitor the difference
between the reverse recovery charge values of the GTOs, (∆Qs)
must be kept to a minimum.
TURN-OFF BY GATE COMMUTATION
At turn-off, the voltage mis-sharing,
∆V,
is very dependent on Itm,
Cs, and
∆t
gs
.
∆V
= I
tm
.
∆t
gs
/Cs
SELECTING THE VALUE OF Cs
Cs must be sized for (a) minimising delay time variations at turn-
on, (b) conventional GTO gate commutated turn-off and (c) GTO
reverse recovery, if appropriate. The requirement for turn-off
usually dominates. Clearly, the aim must be to reduce the value
of Cs to as low a value as permitted by the application and the
GTO specification. Using a gate drive which delivers a higher
turn-off gate current rate can help to reduce the required value
of Cs.
I
TM
This is the current being turned-off. This current is relatively low
in a current source inverter. By contrast, currents can be very
high in a voltage source inverter and this leads to high values of
∆V.
Consequently, Cs values must be high to compensate.
Fig. 3 Simplified version of gdu turn-off section - in reality 10x 470
µ
F capacitors used
2/5
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AN5177 Application Note
Fig. 4 Loop inductance and dynamic resistance
IMPROVED GATE DRIVE UNIT TURN-OFF
PERFORMANCE
A new gate drive unit(GDU) has been designed which gives the
GTO improved turn-off performance.
Figure 3 shows a simplified circuit of the turn-off section of the
GDU. The turn-off current pulse is achieved by charging a
parallel bank of low inductance capacitors to 20 volts and
discharging into the GTO gate using MOSFET switches. To
achieve a high current and high dIg/dt a low loop inductance is
required.
increased at high operating frequencies by the ‘skin’ effect i.e.
the tendency of high frequency currents to flow near the outer
surface of a conductor. For this reason, strip line with its high
surface area to cross sectional area ratio is an ideal choice for
high current pulses with fast rising and falling edges.
PERFORMANCE IMPROVEMENTS IN THE GTO
AT GATE TURN-OFF
The performance improvements reported below are for a standard
DGT409 which is a reverse blocking GTO type.
In measuring the effects on GTO performance of high dig/dt gate
turn off, three areas are of key importance.
1. The effect on turn-off switching loss.
2. The effect on turn-off current rating, Itcm.
3. The effect on storage time.
1. Figure 5 shows the increase in turn-off switching loss with
dI
gt
/dt However, at high dI
gt
/dt values, above about 50A/µS,
the rate of increase is low so the loss penalty for using high
dIgt/dt values is small.
2. The effect on I
tcm
is beneficial. The high dI
gt
/dt and peak turn-
off current ensure that the elements most remote from the
gate connection on the edge of the silicon slice receive more
gate current than normal. This means that the storage time
variations between the elements is much less and sharing of
turned off current between elements is much better.
Figure 6 shows the variation of I
TCM
with Cs for normal and high
dI
GT
/dt.
3. The reduction in storage time, t
gs
, is very marked between
dI
gt
/dt = -40A/µs and –250A/µs, typically a factor of 6. It
follows that as
∆t
gs
also reduces by a factor of 6 then Cs can
be reduced by the same factor for the same change in
∆V.
Figure 7. However, by the law of diminishing returns further
LOOP INDUCTANCE AND DYNAMIC RESISTANCE
The relevant parts of the loop inductance and dynamic resistance
are shown in figure 4.
Unfortunately, the physical design of the GTO itself, with its
centre gate and gate termination layout, limits the minimum loop
inductance which can be achieved. However, careful design of
the gate drive PCB and of the interconnecting lead to the GTO
housing has resulted in a great reduction in the overall loop
inductance. For the GTO type DGT409 a loop inductance of less
than 65nH has been achieved. This compares with 500nH for the
conventional GDU and lead switching at 40A/µs and around
15nH for the IGCT.
Conventionally, coaxial type cable is used as the gate lead to
GTOs but the inductance of a normal cable and its terminations
is too high for our application. To minimise the mutual inductance
of a connecting lead pair it is necessary to keep the spacing
between the forward and return lead as small as possible. A
coaxial cable is better than a twisted pair but the strip line is
probably the best. Here the conductors are usually thin copper
sheets separated by a very thin insulating sheet.
The effective inductance of a conductor is, in part, determined by
the operating frequency. The dynamic resistance of a lead is
3/5
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AN5177 Application Note
4500
4000
3500
3000
2500
2000
V
D
= 3000V
V
D
= 4500V
2.0
1.8
Conditions:
V
DM
= 4300V, T
j
= 100˚C
Max. permissible turn-off current, I
TCM
- (kA)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0
– dI
GQ
/dt = 20A/µs
– dI
GQ
/dt = 220A/µs
Turn-off energy loss, E
OFF
- (mJ)
V
D
= 1500V
1500
1000
500
0
0
10
20
30
40
50
60
Rate of rise of reverse gate current, dI
GQ
/dt - (A/µs)
Conditions:
T
j
= 115˚C, R
S
= 10Ω,
I
T
= 800A, C
S
= 2µF
0.5
1.0
1.5
Snubber capacitance, Cs - (µF)
2.0
Fig. 5 Turn-off energy vs rate of rise of reverse
gate current
Fig. 6 Max. permissible turn-off current vs
snubber capacitance
increases in dI
GT
/dt will have much less effect in further
reducing storage time.
4. The reduction in gate turn-off charge Q
gq
is less marked,
typically 40% for a change of dIgt/dt from 40 to 250A/µs. The
consequence of this is that the power output requirement of
the gate drive unit is reduced by 40%. Again for further
increases in dI
GT
/dt the law of diminishing returns applies.
18
Conditions:
T
j
= 100˚C for Cs = 0.1 to 2µF
16
14
Gate storage time, t
gs
- (µs)
– dI
GQ
/dt = 20A/µs
12
10
CONCLUSIONS
Using gate drive circuits with faster rates of rise of gate turn-off
current results in higher turn-off current rating, Itcm. Another
benefit is the reduction in storage time resulting in smaller
sharing capacitors for series connected GTOs. The turn-off
power requirements of the gate drive are less for a GTO
operating with high rates of rise of turn-off current.
The performance improvements described have been achieved
using a relatively low cost gate drive and offer a very cost
effective alternative to the IGCT in many applications.
500
1000
1500
On-state current, I
T
- (A)
2000
8
6
4
– dI
GQ
/dt = 220A/µs
2
0
0
Fig. 7 Gate storgae time vs on-state current
4/5
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