Clock Synthesizer
and Fanout Buffer/Divider
8T49NS010
DATA SHEET
General Description
The 8T49NS010 is a Clock Synthesizer and Fanout Buffer/Divider.
When used with an external crystal, the 8T49NS010 generates high
performance timing geared towards the communications and data-
com markets, especially for applications demanding extremely low
phase noise jitter, such as 10, 40 and 100GE.
The 8T49NS010 provides versatile frequency configurations and
output formats and is optimized to deliver excellent phase noise
performance. The device delivers an optimum combination of high
clock frequency and low phase noise performance, combined with
high power supply noise rejection.
The 8T49NS010 supports two types of output levels.
FORMAT #1
Outputs
provide an output level with 750mV typical swing, and
requires external DC termination.
FORMAT #2 Outputs
provide a
similar swing level which does not require DC termination.
The device can be configured through an
serial interface and is
offered in a lead-free (RoHS6) 56-pin VFQFN package.
The extended temperature range supports telecommunication and
networking end equipment requirements.
I
2
C
Features
•
•
•
•
•
•
•
•
•
•
•
Ten differential outputs
The input operates in full differential mode (LVDS, LVPECL) or
single-ended LVCMOS mode
Can be driven from a crystal or differential clock
Support of output power-down
Excellent clock output phase noise
Output Frequency
Single-side Band Phase Noise
Offset
100kHz
156.25MHz
-144 dBc/Hz
Phase Noise RMS, 12kHz to 20MHz integration range:
84fs (typical)
LVCMOS compatible I
2
C serial interface
I
2
C control inputs are 3.3V tolerant
Full 3.3V supply voltage
Lead-free (RoHS 6) 56-pin VFQFN packaging
-40°C to 85°C ambient operating temperature
Additional Ordering Information
Part/Order Number
8T49NS010-156NLGI
Package
56-pin VFQFN
Output Frequency (MHz)
156.25, 312.5, 625, 1250
8T49NS010 REVISION 1 11/19/14
1
©2014 Integrated Device Technology, Inc.
8T49NS010 DATA SHEET
Block Diagram
Filter
CP
CAP_REG CAP_REG2
Loop_Filter_R
Loop_Filter
QCLK0
REF_SEL
CLK_IN
nCLK_IN
XTAL_IN
Osc
XTAL_OUT
FB Divider
Output
Frequency
Divider
0
Pulldown
nQCLK0
QCLK1
1
Pre-
Divider
PD
VCO
nQCLK1
QCLK2
nQCLK2
QCLK3
nQCLK3
QCLK4
nQCLK4
QCLK5
nQCLK5
QCLK6
Pulldown
Pullup/
Pulldown
SDATA
SCLK
FB_SEL
N0
N1
Pullup
Pullup
I
2
C
Controller
nQCLK6
Register
QCLK7
nQCLK7
QCLK8
nQCLK8
QCLK9
nQCLK9
Pulldown
Pullup
Pullup
OUTPUT TYPE
Pulldown
8T49NS010 Functional Block Diagram
CLOCK SYNTHESIZER AND FANOUT BUFFER/DIVIDER
2
REVISION 1 11/19/14
8T49NS010 DATA SHEET
Pin Assignment
nQCLK9
nQCLK8
nQCLK7
nQCLK6
nQCLK5
V
DD_CLK
V
DD_CLK
QCLK9
QCLK8
QCLK7
QCLK6
QCLK5
nc
V
SS_I2C
SCLK
SDATA
nCLK_IN
CLK_IN
43
44
45
46
47
48
49
50
51
52
53
54
55
56
42 41 40 39 38 37 36 35 34 33 32 31 30 29
28
27
26
25
24
23
nc
V
DD_A
V
EE_A
Loop_Filter
Loop_Filter_R
BIAS_CAPR
BIAS_CAP
V
DD_A2
V
SS_A2
V
DD_LC_IN
V
SS_FB
V
DD_FB
V
SS_CP
CP
V
DD_CP
22
21
20
19
18
17
16
15
V
DD_I2C
REF_SEL
CAP
V
DD_XTAL
XTAL_IN
XTAL_OUT
V
SS_XTAL
FB_SEL
OUTPUT TYPE
8T49NS010
1
QCLK0
2
3
V
DD_CLK
4
QCLK1
5
6
QCLK2
7
8
9
QCLK3
10 11 12 13 14
V
DD_CLK
N0
3
n
QCLK0
n
QCLK1
n
QCLK2
n
QCLK3
QCLK4
56-pin 8mm x 8mm VFQFN Package
Pin Description and Pin Characteristic Tables
Table 1.
Pin Descriptions
1
Number
1
2
3
4
5
6
7
8
9
10
11
12
REVISION 1 11/19/14
Name
QCLK0
nQCLK0
V
DD_CLK
QCLK1
nQCLK1
QCLK2
nQCLK2
V
DD_CLK
QCLK3
nQCLK3
QCLK4
nQCLK4
Output
Differential clock output pair. FORMAT #1 or FORMAT #2 output levels.
Output
Power
Output
Differential clock output pair. FORMAT #1 or FORMAT #2 output levels.
Output
Output
Differential clock output pair. FORMAT #1 or FORMAT #2 output levels.
Output
Power
Output
Differential clock output pair. FORMAT #1 or FORMAT #2 output levels.
Output
Output
Differential clock output pair. FORMAT #1 or FORMAT #2 output levels.
Output
CLOCK SYNTHESIZER AND FANOUT BUFFER/DIVIDER
Power Supply Voltage (3.3V).
Power Supply Voltage (3.3V).
Type
Description
n
QCLK4
N1
8T49NS010 DATA SHEET
Table 1.
Pin Descriptions
1
(Continued)
Number
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Name
N0
N1
V
DD_CP
CP
V
SS_CP
V
DD_FB
V
SS_FB
V
DD_LC_IN
V
SS_A2
V
DD_A2
BIAS_CAP
BIAS_CAPR
Loop_Filter_R
Loop_Filter
V
EE_A
V
DD_A
NC
NC
nQCLK5
QCLK5
nQCLK6
QCLK6
V
DD_CLK
nQCLK7
QCLK7
nQCLK8
QCLK8
V
DD_CLK
nQCLK9
QCLK9
V
SS_I2C
SCLK
SDATA
Power
Power
Unused
Unused
Output
Differential clock output pair. FORMAT #1 or FORMAT #2 output levels.
Output
Output
Differential clock output pair. FORMAT #1 or FORMAT #2 output levels.
Output
Power
Output
Differential clock output pair. FORMAT #1 or FORMAT #2 output levels.
Output
Output
Differential clock output pair. FORMAT #1 or FORMAT #2 output levels.
Output
Power
Output
Differential clock output pair. FORMAT #1 or FORMAT #2 output levels.
Output
Power
Input
I/O
Pullup
Pullup
Power Supply Ground for I
2
C. Return for Pin 48 V
DD_I2C
.
I
2
C clock input. LVCMOS interface levels.
I
2
C data Input/Output: LVCMOS interface levels. Open Drain Pin.
Power Supply Voltage (3.3V).
Power Supply Voltage (3.3V).
Input
Input
Power
Output
Power
Power
Power
Power
Power
Power
Type
Pullup
Pullup
Description
Output Divider. Refer to
Table 4C.
Output Divider. Refer to
Table 4C.
Power Supply Voltage to Charge Pump (3.3V).
Charge Pump.
Power Supply Ground for Charge Pump - Return for V
DD_CP
.
Power Supply Voltage to Feedback Divider (3.3V).
Power Supply Ground to Feedback Divider (3.3V). Return for V
DD_FB
.
Power Supply Voltage for LC Interface. (3.3V).
Power Supply Ground for VCO.
Power Supply Voltage for VCO.
Bias Capacitor.
Bias Capacitor Return.
Loop Filter Return.
Loop Filter Capacitor.
Power Supply ground for VCO. Return for V
DD_A
pin 28.
Power Supply for VCO.
No internal connection.
No internal connection.
CLOCK SYNTHESIZER AND FANOUT BUFFER/DIVIDER
4
REVISION 1 11/19/14
8T49NS010 DATA SHEET
Table 1.
Pin Descriptions
1
(Continued)
Number
46
47
48
49
50
51
52
53
54
55
56
Name
nCLK_IN
CLK_IN
V
DD_I2C
REF_SEL
CAP
V
DD_XTAL
XTAL_IN
XTAL_OUT
V
SS_XTAL
FB_SEL
OUTPUT
TYPE
V
EE_EP
Power
Input
Input
Pulldown
Pulldown
Power
Input
Input
Power
Input
Pulldown
Type
Pullup/
Pulldown
Pulldown
Description
Inverting differential clock input. Internal resistor bias to V
DD_x
/2.
Non-inverting differential clock input.
Power Supply Voltage for I
2
C.
Selects between XTAL and CLK. 0 select Xtal (with x2)and 1 selects CLK
input. Refer to
Table 4A.
LVCMOS interface levels.
Bypass capacitor for internal reference. Should connect cap between this
pin and V
DD_I2C
pin 48.
Power Supply for crystal.
Crystal oscillator interface, XTAL_IN is the input.
Crystal oscillator interface, XTAL_OUT is the output.
Power Supply Ground for XTAL circuit. Return for pin 51
Feedback Divider select. Refer to
Table 4B.
LVCMOS interface levels.
Selects between FORMAT #1 or FORMAT #2 (with no DC termination)
output levels. “0” selects FORMAT #2 and “1” selects FORMAT #1 type
output structure. Refer to
Table 5K.
LVCMOS interface levels.
Negative supply. Exposed pad must be connected to ground. Return for all
outputs and core supplies Pins 3, 8, 20, 35, 40.
ePad
Power
NOTE 1.Pulldown and
Pullup
refer to internal input resistors. See
Table 2,
Pin Characteristics,
for typical values
Table 2.
Input Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
3.5
51
51
Maximum
Units
pF
k
k
Table 3.
Output Characteristics
Symbol
R
OUT
Parameter
Output
Impedance
SDATA
Test Conditions
V
DD_I2C
= 3.3V ± 5%
Minimum
Typical
60
Maximum
Units
REVISION 1 11/19/14
5
CLOCK SYNTHESIZER AND FANOUT BUFFER/DIVIDER
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