74ALVC162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26Ω Series
Resistors in Outputs
September 2001
Revised February 2002
74ALVC162835
Low Voltage 18-Bit Universal Bus Driver
with 3.6V Tolerant Inputs/Outputs
and 26
Ω
Series Resistors in Outputs
General Description
The ALVC162835 low voltage 18-bit universal bus driver
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (I
n
) to Outputs (O
n
) on
a Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The ALVC162835 is designed with 26
Ω
series resistors in
the outputs. This design reduces noise in applications such
as memory address drivers, clock drivers, and bus trans-
ceivers/transmitters.
The 74ALVC162835 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The 74ALVC162835 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
Compatible with PC100 DIMM module specifications
s
1.65V to 3.6V V
CC
specifications provided
s
3.6V tolerant inputs and outputs
s
26
Ω
series resistors in outputs
s
t
PD
(CLK to O
n
)
5.4 ns max for 3.0V to 3.6V V
CC
6.3 ns max for 2.3V to 2.7V V
CC
9.2 ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high impedance state during power up or power
down, OE should be tied to V
CC
through a pulldown resistor; the minimum
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Order Number
74ALVC162835T
Package
Number
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2002 Fairchild Semiconductor Corporation
DS500646
www.fairchildsemi.com
74ALVC162835
Connection Diagram
Pin Descriptions
Pin Names
OE
LE
CLK
I
1
- I
18
O
1
- O
18
Description
Output Enable Input (Active LOW)
Latch Enable Input
Clock Input
Data Inputs
3-STATE Outputs
Truth Table
Inputs
OE
H
L
L
L
L
L
L
LE
X
H
H
L
L
L
L
CLK
X
X
X
I
n
X
L
H
L
H
X
X
Outputs
O
n
Z
L
H
L
H
O
0
(Note 2)
O
0
(Note 3)
↑
↑
H
L
H
=
Logic HIGH
L
=
Logic LOW
X
=
Don’t Care, but not floating
Z
=
High Impedance
↑ =
LOW-to-HIGH Clock Transition
Note 2:
Output level before the indicated steady-state input conditions
were established provided that CLK was HIGH before LE went LOW.
Note 3:
Output level before the indicated steady-state input conditions
were established.
Logic Diagram
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2
74ALVC162835
Absolute Maximum Ratings
(Note 4)
Supply Voltage (V
CC
)
DC Input Voltage (V
I
)
Output Voltage (V
O
) (Note 5)
DC Input Diode Current (I
IK
)
V
I
<
0V
DC Output Diode Current (I
OK
)
V
O
<
0V
DC Output Source/Sink Current
(I
OH
/I
OL
)
DC V
CC
or Ground Current per
Supply Pin (I
CC
or Ground)
Storage Temperature Range (T
STG
)
−
0.5V to
+
4.6V
−
0.5V to
+
4.6V
−
0.5V to V
CC
+
0.5V
−
50 mA
−
50 mA
±
50 mA
±
100 mA
−
65
°
C to
+
150
°
C
Recommended Operating
Conditions
(Note 6)
Power Supply
Operating
Input Voltage
Output Voltage (V
O
)
Free Air Operating Temperature (T
A
)
Minimum Input Edge Rate (
∆
t/
∆
V)
V
IN
=
0.8V to 2.0V, V
CC
=
3.0V
10 ns/V
Note 4:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The Recommended Operating Conditions tables will define the condi-
tions for actual device operation.
Note 5:
I
O
Absolute Maximum Rating must be observed.
Note 6:
Floating or unused pin (inputs or I/O's) must be held HIGH or LOW.
1.65V to 3.6V
0V to V
CC
0V to V
CC
−
40
°
C to
+
85
°
C
DC Electrical Characteristics
Symbol
V
IH
Parameter
HIGH Level Input Voltage
Conditions
V
CC
(V)
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
V
IL
LOW Level Input Voltage
1.65 - 1.95
2.3 - 2.7
2.7 - 3.6
V
OH
HIGH Level Output Voltage
I
OH
= −100 µA
I
OH
= −2
mA
I
OH
= −4
mA
I
OH
= −6
mA
I
OH
= −8
mA
I
OH
= −12
mA
V
OL
LOW Level Output Voltage
I
OL
=
100
µA
I
OL
=
2 mA
I
OL
=
4 mA
I
OL
=
6 mA
I
OL
=
8 mA
I
OL
=
12 mA
I
I
I
OZ
I
CC
∆I
CC
Input Leakage Current
3-STATE Output Leakage
Quiescent Supply Current
Increase in I
CC
per Input
0
≤
V
I
≤
3.6V
0
≤
V
O
≤
3.6V
V
I
=
V
CC
or GND, I
O
=
0
V
IH
=
V
CC
−
0.6V
1.65 - 3.6
1.65
2.3
2.3
3.0
2.7
3.0
1.65 - 3.6
1.65
2.3
2.3
3.0
2.7
3
3.6
3.6
3.6
3 - 3.6
V
CC
- 0.2
1.2
1.9
1.7
2.4
2
2
0.2
0.45
0.4
0.55
0.55
0.6
0.8
±5.0
±10
40
750
µA
µA
µA
µA
V
V
Min
0.65 x V
CC
1.7
2.0
0.35 x V
CC
0.7
0.8
V
V
Max
Units
3
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74ALVC162835
AC Electrical Characteristics
T
A
= −40°C
to
+85°C,
R
L
=
500Ω
Symbol
Parameter
C
L
=
50 pF
V
CC
=
3.3V
±
0.3V
Min
f
CLOCK
t
W
t
S
Clock Frequency
Pulse Width LE High
CLK High or Low
Setup Time
Data Before CLK
↑
Data Before CLK
↓
CLK High
CLK Low
t
H
Hold Time
Data After CLK
↑
Data After LE
↓
f
MAX
Maximum Clock Frequency
Delay
LE to O
CLK to O
t
PZL
, t
PZH
Output Enable Time
t
PLZ
, t
PHZ
Output Disable Time
CLK High
or Low
t
PHL
, t
PLH
Propagation I to O
3.3
3.3
1.7
1.5
1.0
0.7
1.4
150
1.0
1.3
1.4
1.1
1.3
4.2
5.1
5.4
5.5
4.5
Max
150
3.3
3.3
2.1
1.6
1.1
0.6
1.7
150
5.0
5.8
6.1
6.5
4.9
V
CC
=
2.7V
Min
Max
150
3.3
3.3
2.2
1.9
1.3
0.6
1.4
150
1.0
1.3
1.4
1.4
1.0
5.0
5.9
6.3
6.3
4.9
100
1.5
1.5
2.0
1.5
1.5
9.8
9.8
9.2
9.8
7.9
ns
ns
ns
1.0
ns
MHz
C
L
=
30 pF
V
CC
=
2.5V
±
0.2V V
CC
=
1.8V
±
0.15V
Min
Max
150
4.0
4.0
2.5
ns
Min
Max
100
MHz
ns
Units
AC Electrical Characteristics Over Load
(Note 7)
R
L
=
500Ω, V
CC
=
3.3V
±
0.15V
Symbol
Parameter
T
A
= −0°C
to
+85°C
C
L
=
0 pF
Min
t
PHL
, t
PLH
t
PHL
, t
PLH
Propagation Delay Bus to Bus
Propagation Delay Clock to Bus
0.9
1.4
Max
2.0
2.9
Min
1.0
1.9
T
A
= −0°C
to
+65°C
C
L
=
50 pF
Max
4.0
5.0
ns
ns
Units
Note 7:
Characterized only.
Capacitance
Symbol
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Parameter
Control
Data
V
I
=
0V or V
CC
V
I
=
0V or V
CC
V
I
=
0V, or V
CC
Conditions
T
A
= +25°C
V
CC
3.3
3.3
3.3
3.3
2.5
Outputs Disabled f
=
10 MHz, C
L
=
0 pF
3.3
2.5
Typical
3.5
5
7
40
35
14
125
pF
Units
pF
pF
Power Dissipation Capacitance Outputs Enabled f
=
10 MHz, C
L
=
0 pF
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4
74ALVC162835
I
OUT
- V
OUT
Characteristics
I
OH
versus V
OH
FIGURE 1. Characteristics for Output - Pull Up Drive
I
OL
versus V
OL
FIGURE 2. Characteristics for Output - Pull Down Driver
5
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