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FlashFlex MCU
A Microchip Technology Company
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
The SST89E516RDx and SST89V516RDx are members of the FlashFlex family
of 8-bit microcontroller products designed and manufactured with SST’s patented
and proprietary SuperFlash CMOS semiconductor process technology. The split-
gate cell design and thick-oxide tunneling injector offer significant cost and reli-
ability benefits for SST’s customers. The devices use the 8051 instruction set and
are pin-for-pin compatible with standard 8051 microcontroller devices.
Features
• 8-bit 8051-Compatible Microcontroller (MCU) with
Embedded SuperFlash Memory
– Fully Software Compatible
– Development Toolset Compatible
– Pin-For-Pin Package Compatible
• Programmable Watchdog Timer (WDT)
• Programmable Counter Array (PCA)
• Four 8-bit I/O Ports (32 I/O Pins) and
One 4-bit Port
• Second DPTR register
• Low EMI Mode (Inhibit ALE)
• SPI Serial Interface
• Standard 12 Clocks per cycle, the device has an
option to double the speed to 6 clocks per cycle.
• TTL- and CMOS-Compatible Logic Levels
• Brown-out Detection
• Low Power Modes
– Power-down Mode with External Interrupt Wake-up
– Idle Mode
• SST89E516RD2 Operation
– 0 to 40 MHz at 5V
• SST89V516RD2 Operation
– 0 to 33 MHz at 3V
• 1 KByte Internal RAM
• Dual Block SuperFlash EEPROM
– 64 KByte primary block +
8 KByte secondary block
(128-Byte sector size for both blocks)
– Individual Block Security Lock with SoftLock
– Concurrent Operation during
In-Application Programming (IAP)
– Memory Overlay for Interrupt Support during IAP
• Support External Address Range up to 64 KByte
of Program and Data Memory
• Three High-Current Drive Ports (16 mA each)
• Three 16-bit Timers/Counters
• Full-Duplex, Enhanced UART
– Framing Error Detection
– Automatic Address Recognition
• Temperature Ranges:
– Commercial (0°C to +70°C)
– Industrial (-40°C to +85°C)
• Packages Available
– 40-contact WQFN (Port 4 feature not available)
– 44-lead PLCC
– 40-pin PDIP (Port 4 feature not available)
– 44-lead TQFP
• Ten Interrupt Sources at 4 Priority Levels
– Four External Interrupt Inputs
• All non-Pb (lead-free) devices are RoHS compliant
©2011 Silicon Storage Technology, Inc.
www.microchip.com
DS25093A
11/11
FlashFlex MCU
A Microchip Technology Company
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
Product Description
The SST89E516RDx and SST89V516RDx are members of the FlashFlex family of 8-bit microcon-
troller products designed and manufactured with SST’s patented and proprietary SuperFlash CMOS
semiconductor process technology. The split-gate cell design and thick-oxide tunneling injector offer
significant cost and reliability benefits for SST’s customers. The devices use the 8051 instruction set
and are pin-for-pin compatible with standard 8051 microcontroller devices.
The devices come with 72 KByte of on-chip flash EEPROM program memory which is partitioned into
2 independent program memory blocks. The primary Block 0 occupies 64 KByte of internal program
memory space and the secondary Block 1 occupies 8 KByte of internal program memory space.
The 8-KByte secondary block can be mapped to the lowest location of the 64 KByte address space; it
can also be hidden from the program counter and used as an independent EEPROM-like data mem-
ory.
In addition to the 72 KByte of EEPROM program memory on-chip and 1024 x8 bits of on-chip RAM,
the devices can address up to 64 KByte of external program memory and up to 64 KByte of external
RAM.
The flash memory blocks can be programmed via a standard 87C5x OTP EPROM programmer fitted
with a special adapter and the firmware for SST’s devices. During power-on reset, the devices can be
configured as either a slave to an external host for source code storage or a master to an external host
for an in-application programming (IAP) operation. The devices are designed to be programmed in-
system and in-application on the printed circuit board for maximum flexibility. The devices are pre-pro-
grammed with an example of the bootstrap loader in the memory, demonstrating the initial user pro-
gram code loading or subsequent user code updating via the IAP operation. The sample bootstrap
loader is available for the user’s reference and convenience only; SST does not guarantee its function-
ality or usefulness. Chip-Erase or Block-Erase operations will erase the pre-programmed sample code.
©2011 Silicon Storage Technology, Inc.
DS25093A
11/11
2
FlashFlex MCU
A Microchip Technology Company
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
Functional Blocks
8051
CPU Core
ALU,
ACC,
B-Register,
Instruction Register,
Program Counter,
Timing and Control
Oscillator
Interrupt
Control
10 Interrupts
Watchdog Timer
Flash Control Unit
SuperFlash
EEPROM
Primary
Block
64K x8
Secondary
Block
8K x8
RAM
1K x8
8
I/O Port 0
8
Security
Lock
I/O Port 1
8
I/O Port 2
I/O
8
I/O Port 3
I/O
4
I/O Port 4
I/O
I/O
I/O
Timer 0 (16-bit)
Timer 1 (16-bit)
Timer 2 (16-bit)
SPI
PCA
Enhanced
UART
1273 B1.0
Figure 1:
Functional Block Diagram
©2011 Silicon Storage Technology, Inc.
DS25093A
11/11
3
FlashFlex MCU
A Microchip Technology Company
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
Pin Assignments
P1.4 (CEX1 / SS#)
P1.1 (T2 EX)
P1.3 (CEX0)
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
(CEX2 / MOSI) P1.5
(CEX3 / MISO) P1.6
(CEX4 / SCK) P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0#) P3.2
(INT1#) P3.3
(T0) P3.4
(T1) P3.5
1
40
P0.3 (AD3)
P1.2 (ECI)
P1.0 (T2)
VDD
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
Top View
(contacts facing down)
EA#
ALE/PROG#
PSEN#
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
(WR#) P3.6
(RD#) P3.7
XTAL2
XTAL1
VSS
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
1273 40-wqfn QI P1.0
Figure 2:
Pin Assignments for 40-Contact WQFN
©2011 Silicon Storage Technology, Inc.
DS25093A
11/11
4
FlashFlex MCU
A Microchip Technology Company
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
(T2) P1.0
(T2 EX) P1.1
(ECI) P1.2
(CEX0) P1.3
(CEX1 / SS#) P1.4
(CEX2 / MOSI) P1.5
(CEX3 / MISO) P1.6
(CEX4 / SCK) P1.7
RST
(RXD) P3.0
(TXD) P3.1
(INT0#) P3.2
(INT1#) P3.3
(T0) P3.4
(T1) P3.5
(WR#) P3.6
(RD#) P3.7
XTAL2
XTAL1
VSS
1
2
3
4
5
6
7
40
39
38
37
36
35
VDD
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA#
ALE/PROG#
PSEN#
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
1273 40-pdip PI P2.0
34
40-pin PDIP
8 Top View 33
32
9
31
10
11
12
13
14
15
16
17
18
19
20
30
29
28
27
26
25
24
23
22
21
Figure 3:
Pin Assignments for 40-pin PDIP
©2011 Silicon Storage Technology, Inc.
DS25093A
11/11
5
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