CML Microcircuits
COMMUNICA
TION SEMICONDUCTORS
D/7861_FI-1.x/2 June 2012
CMX7861
®
FirmCODEC
Advance Information
DATASHEET
7861FI-1.x Programmable Baseband Interface
Features
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Features Cont.
Low-power 3.0V to 3.6V operation
Multiple power-saving options
Small 64-pin VQFN Package
Evaluation support
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PE0601-7861 Evaluation kit
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PE0002 Interface card
Dual Channel Codecs
Can operate in modem or codec mode
Two ADCs 16 bit
Two DACs 14 bit
Programmable input and output gain
Differential/single ended inputs/outputs
Digital Channel Filters
Two fully-programmable digital filters
Filter design and configuration support
Auxiliary ADCs
Four 10-bit DACs
Autonomous RAMDAC sequencer
Auxiliary ADC
One 10-bit ADC with four-input MUX
ADC averaging, trip on high/low ‘watch’ modes
Auxiliary GPIO
Four programmable input/outputs
Auxiliary Synthesised Clock Generators
Two programmable clock outputs
C-BUS Host Serial Interface
SPI-like with register addressing
Read/write 128-byte FIFOs and data buffers
Streamline transfers, low host service latency
Master SSP Interface
External slave device control
Serial Flash connection
Pass-through (Thru-port) mode expands host
C-BUS/SPI capacity
Dual Channel Codec
Channel 1 ADC
Channel 2 ADC
Channel 3 DAC
Applications
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General-purpose DSP analogue/digital
interface
Sensors
Control systems
Telemetry/SCADA/data modems
High Performance Narrowband Data Radio
DMR
APCO P25
Software Defined Radio (SDR)
6.25kHz to 25kHz RF channel spacings
worldwide compatibility e.g. ETSI, FCC,
ARIB, FCC Part 90 per spectral efficiency
requirements
High Performance I/Q Radio Interface
Tx and Rx: ‘direct connect’ to zero IF
transceiver
Simple external RC filters
Digital filter configurable for multiple RF
channel spacings (Rx), Default is for DMR
I/Q trims
Programmable Digital Filter 1
Programmable Digital Filter 2
Channel 4 DAC
Analogue
System/Signals
Auxiliary Operations
ADC
Sample Buffers
ADC/DAC Sync
Clock Generation
Power Management
FIFO
DACs
‘Smart’
Function
Engine
Configuration
C-BUS
Registers
DSP
Microcontroller
This document contains:
Datasheet
User
Manual
GPIO
Clocks Synths
Function Image™
Aux SSP
CMX7861
FirmCODEC®
2012 CML Microsystems Plc
CMX7861 FirmCODEC
®
Programmable Baseband Interface
CMX7861
1
1.1
Brief Description
General
®
The CMX7861 FirmCODEC is a general-purpose, dual-channel baseband interface device for use in
DSP-based systems. The device is a combination of codec, embedded signal processing and auxiliary
system support functions that, together, allow simple interfacing to analogue and digital systems.
Single-ended and differential interface options are provided and I/Q-based operation is supported. The
device can also be used in radio systems operating with channel bandwidths up to 50kHz, interfacing RF
devices to baseband DSP/microcontroller, performing the main data conversion and auxiliary operations
for monitoring and control.
Fully-programmable on-chip digital channel filters can be utilised for signal conditioning purposes.
Intelligent auxiliary ADC, DAC and GPIO sub-systems perform valuable functions and minimise host
interaction and host I/O resources. Two synthesised system clock generators develop clock signals for
off-chip use. The C-BUS/SPI master interface expands host C-BUS/SPI ports to control external devices.
The CMX7861 utilises CML’s proprietary
FirmASIC
component technology that enables on-chip sub-
systems to be configured by a Function Image™ data file, which is uploaded during device initialisation
and defines the device's function and feature set. The Function Image™ can be loaded automatically from
a host µC over the C-BUS serial interface or from an external memory device. The device's functions and
features can be enhanced by subsequent Function Image™ releases, facilitating in-the-field upgrades.
The CMX7861 operates from a 3.3V supply and includes selectable power saving modes. It is available in
a 64-VQFN package.
1.2
Codec and Modem Modes
Two general modes of operation are supported: codec mode and modem mode.
Codec mode is intended for applications where a general purpose codec is required. When in codec
mode the CMX7861 will provide digital-to-analogue and analogue-to-digital conversion, producing a flat
pass band over the sampled bandwidth. Simple programmable transmit and receive filter options are
provided but there are no signal interpolation facilities available, and the maximum sample rate is limited.
Modem mode is suited to applications where the CMX7861 is used to transmit modulated data and
receive that data. Modem mode provides a transmit signal interpolator which will aid in the modulation
process by converting mapped symbols to a filtered, modulated output. Receive channel filters are also
provided, however filter design is more complex than codec mode as ADC and DAC roll off need to be
considered when designing filters. Modem mode is, in general, more efficient than codec mode and is
capable of providing a higher sample rate.
This datasheet is the first part of a two-part document.
2012 CML Microsystems Plc
Page 2
D/7861_FI-1.x/2
CMX7861 FirmCODEC
®
Programmable Baseband Interface
CMX7861
CONTENTS
Section
1
Page
Brief Description ...................................................................................................................... 2
1.1
General ......................................................................................................................... 2
1.2
Codec and Modem Modes ........................................................................................... 2
1.3
History........................................................................................................................... 5
Block Diagrams ....................................................................................................................... 6
Signal/Pin List .......................................................................................................................... 7
3.1
Power Supply Signal Definitions .................................................................................. 9
PCB Layout Guidelines and Power Supply Decoupling .................................................... 10
External Components ........................................................................................................... 11
5.1
Xtal Interface .............................................................................................................. 11
5.2
C-BUS Interface ......................................................................................................... 11
5.3
Signal Output .............................................................................................................. 12
5.3.1 Output Signal Routing .......................................................................................... 12
5.3.2 Output Reconstruction Filter – (I/Q mode) ........................................................... 13
5.3.3 Output Reconstruction Filter – Single-ended Outputs ......................................... 14
5.4
Signal Input ................................................................................................................. 14
5.4.1 Input Signal Routing ............................................................................................. 14
5.4.2 Input Anti-alias Filter (I/Q mode) .......................................................................... 16
5.4.3 Input Anti-alias Filter (Inputs 3 and 4) .................................................................. 16
General Description .............................................................................................................. 18
6.1
CMX7861 Features .................................................................................................... 18
6.2
Signal Interfaces ......................................................................................................... 19
Detailed Descriptions ............................................................................................................ 21
7.1
Xtal Frequency ........................................................................................................... 21
7.2
Host Interface ............................................................................................................. 21
7.2.1 C-BUS Operation ................................................................................................. 21
7.3
Function Image™ Loading ......................................................................................... 24
7.3.1 FI Loading from Host Controller ........................................................................... 24
7.3.2 FI Loading from Serial Memory............................................................................ 26
7.4
Device Control ............................................................................................................ 27
7.4.1 Normal Operation Overview ................................................................................. 27
7.4.2 Basic Tx and Rx Operation .................................................................................. 28
7.4.3 Device Configuration (Using the Programming Register) .................................... 31
7.4.4 Device Configuration (Using dedicated registers) ............................................... 31
7.4.5 Interrupt Operation ............................................................................................... 31
7.4.6 Signal Control....................................................................................................... 32
7.4.7 Tx Mode Processing ............................................................................................ 32
7.4.8 Rx Mode Processing ............................................................................................ 33
7.4.9 Duplex Mode ........................................................................................................ 34
7.4.10 Other Modes ........................................................................................................ 34
7.4.11 Data Transfer ....................................................................................................... 35
7.4.12 Sample Format..................................................................................................... 37
7.4.13 Data Buffering ...................................................................................................... 41
7.4.14 Managing Data Transfer ...................................................................................... 42
7.4.15 GPIO Pin Operation ............................................................................................. 42
2
3
4
5
6
7
2012 CML Microsystems Plc
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CMX7861 FirmCODEC
®
Programmable Baseband Interface
CMX7861
7.5
7.6
7.7
7.8
7.9
8
7.4.16 Auxiliary ADC Operation ...................................................................................... 42
7.4.17 Auxiliary DAC/RAMDAC Operation ..................................................................... 43
7.4.18 SPI Thru-Port ....................................................................................................... 43
Digital System Clock Generators ............................................................................... 44
7.5.1 Main Clock Operation .......................................................................................... 44
7.5.2 System Clock Operation ...................................................................................... 44
Signal Level Optimisation ........................................................................................... 45
7.6.1 Transmit Path Levels ........................................................................................... 45
7.6.2 Receive Path Levels ............................................................................................ 46
Application Information ............................................................................................... 46
7.7.1 ADC and DAC Filters ........................................................................................... 46
7.7.2 ADC and DAC Sample Timing Synchronisation .................................................. 46
Codec And Modem Mode Descriptions ...................................................................... 47
7.8.1 Codec Mode ......................................................................................................... 47
7.8.2 Modem Mode ....................................................................................................... 48
C-BUS Register Summary.......................................................................................... 49
Performance Specification ................................................................................................... 50
8.1
Electrical Performance ............................................................................................... 50
8.1.1 Absolute Maximum Ratings ................................................................................. 50
8.1.2 Operating Limits ................................................................................................... 50
8.1.3 Operating Characteristics .................................................................................... 51
8.1.4 Performance Characteristics................................................................................ 55
8.2
C-BUS Timing ............................................................................................................. 56
8.3
Packaging ................................................................................................................... 57
Page
Signal/Pin List .................................................................................................................... 7
Definition of Power Supply and Reference Voltages ......................................................... 9
BOOTEN Pin States ........................................................................................................ 24
FIFO Transfer Summary .................................................................................................. 36
Rx ADC1/ADC2 sample blocks........................................................................................ 37
Rx ADC1/ADC2, Phase/Magnitude sample blocks ......................................................... 39
Tx DAC1/DAC2 sample blocks ........................................................................................ 41
C-BUS Registers .............................................................................................................. 49
Page
Table
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Figure
Figure 1 Overall Block Diagram ...................................................................................................... 6
Figure 2 CMX7861 Power Supply and De-coupling ..................................................................... 10
Figure 3 Recommended External Components - Xtal Interface ................................................... 11
Figure 4 Recommended External Components - C-BUS Interface .............................................. 11
Figure 5 Analogue Output Routing ............................................................................................... 13
Figure 6 Recommended External Components – I/Q Output Reconstruction Filter ..................... 14
Figure 7 Recommended External Components - Single-ended Outputs Reconstruction Filter ... 14
Figure 8 Analogue Input Routing .................................................................................................. 15
Figure 9 Input Anti-alias FIlter: Inputs 1 and 2 .............................................................................. 16
Figure 10 Input Anti-alias FIlter: Inputs 3 and 4 ............................................................................ 16
Figure 11 CMX7861 Interface to Analogue Systems .................................................................... 19
Figure 12 CMX7861 I/Q Tx, I/Q Rx ............................................................................................... 19
2012 CML Microsystems Plc
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D/7861_FI-1.x/2
CMX7861 FirmCODEC
®
Programmable Baseband Interface
CMX7861
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
CMX7861 Two-point Tx, Classic FM Limiter-Discriminator Rx .................................... 20
CMX7861 Polar Tx, Amplitude and Phase Rx .............................................................. 20
Basic C-BUS Transactions ........................................................................................... 22
C-BUS Data Streaming Operation ................................................................................ 23
FI Loading from Host .................................................................................................... 25
FI Loading from Serial Memory .................................................................................... 26
Tx Mode Processing ..................................................................................................... 32
Rx Mode Processing ..................................................................................................... 33
Constellation Diagram – no frequency or phase error .................................................. 34
Constellation Diagram – phase error ............................................................................ 34
Constellation Diagram – frequency error ...................................................................... 34
Received Eye Diagram ................................................................................................. 35
Tx and Rx Data FIFOs .................................................................................................. 36
Main Clock Generation ................................................................................................. 44
Digital System Clock Generation Schemes .................................................................. 45
ADC/DAC Sample Timing Synchronisation .................................................................. 47
C-BUS Timing ............................................................................................................... 56
Mechanical Outline of 64-pin VQFN (Q1) ..................................................................... 57
Information in this datasheet should not be relied upon for final product design. It is always recommended
that you check for the latest product datasheet version from the CML website: [www.cmlmicro.com].
1.3
History
Changes
Note 32 expanded and Note 48 added in section 8.1.3, to cover dc operation
First issue
Date
May 2012
Dec 2011
Version
2
1
2012 CML Microsystems Plc
Page 5
D/7861_FI-1.x/2
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