CMX7262
CML Microcircuits
COMMUNICA
TION SEMICONDUCTORS
TWELP Vocoder
D/7262_FI-1.x/4 August 2013
DATASHEET
7262 FI-1.x Professional Radio Vocoder
Advance Information
Features
High-performance, low bit rate vocoder using
TWELP (Tri-wave Excited Linear Prediction)
technology
Crystal clear voice and excellent performance
in real-life radio operation
Excellent performance providing natural-
sounding speech and high quality non-voiced
signals such as emergency services sirens
Half-duplex operation
FEC built in to each vocoder frame
Noise Reduction
Integral voiceband audio codec (No external
DSP or codecs required)
C-BUS host serial interface
o
Streaming input and output registers to
streamline transfers and relax host service
latency
Signal routing:
o
Choice of input sources – C-BUS transfer
from host, analogue audio input
o
Choice of output sources – C-BUS transfer
to host, analogue audio output
Auxiliary functions
o
GPIOs
o
Two differential audio outputs
o
Single-ended speaker output
o
Analogue input/output gain adjustment
o
Analogue input multiplexer
o
Analogue output multiplexer
Low power 3.3V operation with powersave
functions
Small 64-pin VQFN package
Applications
Half duplex digital radio systems
Personal area network voice links
Secure digital voice communications
Secure door access
Wireless PBX
VoIP applications
Digital Software Defined Radio (SDR)
GPIOs
Registers
Analogue In
ADC
Digital
Filters
FIFO
Analogue Out
DAC
Digital
Filters
Configuration
Function
Image™
C-BUS
Host
µC
CMX7262
Professional Radio Vocoder - TWELP
TWELP
Vocoder
3.3V
3.3V
2013 CML Microsystems Plc
TWELP Vocoder
CMX7262
1
Brief Description
The CMX7262 TWELP Vocoder IC is a device supporting a Tri-Wave Excited Linear Prediction (TWELP)
vocoder functionality in a single chip. The CMX7262 is capable of encoding analogue voice into TWELP-
encoded frames. It is capable of decoding TWELP-encoded frames back to analogue voice.
Input and output signals may be passed through the C-BUS interface, or the on-chip analogue-to-digital
and digital-to-analogue converters (ADC/DAC).
The CMX7262 is designed to be flexible. However, it interfaces directly to the CMX7141 modem and the
two can used together to build a dPMR radio.
The device utilises CML’s proprietary
FirmASIC
component technology. On-chip sub-systems are
configured by a Function Image™ data file that is uploaded during device initialisation and defines the
device's function and feature set. The Function Image™ can be loaded automatically from a host
microcontroller over the C-BUS serial interface or from an external memory device. The device's functions
and features can be enhanced by subsequent Function Image™ releases, facilitating in-the-field
upgrades.
The CMX7262 operates from a 3.3V supply and includes selectable power saving modes. It is available in
a 64-VQFN (Q1) and 64-LQFP (L9) packages.
Note that text shown in pale grey indicates features that will be supported in future versions of the device.
This Data Sheet is the first part of a two-part document.
2013 CML Microsystems Plc
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TWELP Vocoder
CMX7262
CONTENTS
Section
1
2
3
4
5
Page
Brief Description ...................................................................................................................... 2
Block Diagram .......................................................................................................................... 6
2.1
TWELP Vocoder ........................................................................................................... 6
Signal List................................................................................................................................. 7
3.1
Signal Definitions ........................................................................................................ 10
PCB Layout Guidelines and Power Supply Decoupling .................................................... 11
External Components............................................................................................................ 12
5.1
Xtal Interface............................................................................................................... 12
5.2
C-BUS Interface.......................................................................................................... 12
5.3
Serial Port Interface .................................................................................................... 13
5.4
Audio Output ............................................................................................................... 13
5.4.1 Audio Output Routing ........................................................................................... 13
5.4.2 Audio Output Reconstruction Filter ...................................................................... 14
5.5
Audio Input .................................................................................................................. 16
5.5.1 Audio Input Routing .............................................................................................. 16
5.5.2 Differential Audio Input ......................................................................................... 16
5.5.3 Single-Ended Audio Input Interface ..................................................................... 16
5.6
GPIO Pins ................................................................................................................... 17
General Description............................................................................................................... 18
6.1
CMX7262 Features..................................................................................................... 18
6.2
Signal Interfaces ......................................................................................................... 18
6.3
System Design............................................................................................................ 19
6.4
Xtal Frequency............................................................................................................ 22
6.5
Host Interface ............................................................................................................. 22
6.5.1 C-BUS Operation ................................................................................................. 22
6.6
Function Image™ Loading.......................................................................................... 25
6.6.1 FI Loading from Host Controller ........................................................................... 25
6.6.2 FI Loading from Serial Memory ............................................................................ 27
6.7
TWELP Coding Format ............................................................................................. 28
6.8
Vocoder Frame / Packet Sizes ................................................................................... 28
6.8.1 TWELP Packed Data Format .............................................................................. 30
6.9
Data Transfer Using C-BUS Interface ........................................................................ 33
6.10
Noise Reduction ......................................................................................................... 37
6.11
Noise Gate .................................................................................................................. 37
6.12
Device Control ............................................................................................................ 37
6.12.1 Normal Operation Overview ................................................................................. 37
6.12.2 Vocoder Operation ............................................................................................... 38
6.12.3 Device Configuration (Using the Programming Register) .................................... 41
6.12.4 Device Configuration (Using dedicated registers) ................................................ 41
6.12.5 Interrupt Operation ............................................................................................... 41
6.13
Signal Level Optimisation ........................................................................................... 42
6.13.1 Audio Output Path Levels..................................................................................... 42
6.13.2 Audio Input Path Levels ....................................................................................... 42
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2013 CML Microsystems Plc
TWELP Vocoder
CMX7262
6.14
7
C-BUS Register Summary.......................................................................................... 43
Performance Specification ................................................................................................... 44
7.1
Electrical Performance ............................................................................................... 44
7.1.1 Absolute Maximum Ratings ................................................................................. 44
7.1.2 Operating Limits ................................................................................................... 44
7.1.3 Operating Characteristics..................................................................................... 45
7.1.4 Parametric Performance ...................................................................................... 48
7.2
C-BUS Timing ............................................................................................................. 49
7.3
Packaging ................................................................................................................... 50
Page
Definition of Power Supply and Reference Voltages........................................................ 10
BOOTEN Pin States ......................................................................................................... 25
Packet Sizes..................................................................................................................... 29
C-BUS Registers .............................................................................................................. 43
Page
Table
Table 1
Table 2
Table 3
Table 4
Figure
Figure 1 Block Diagram ................................................................................................................... 6
Figure 2 CMX7262 Power Supply and De-coupling ...................................................................... 11
Figure 3 Recommended External Components – Xtal Interface................................................... 12
Figure 4 Recommended External Components – C-BUS Interface.............................................. 12
Figure 5 Interfacing the CMX7262 to Serial Memory .................................................................... 13
Figure 6 Analogue Audio Output Routing...................................................................................... 14
Figure 7 Recommended External Components – ANAOUT1/ANAOUT2 Reconstruction Filter... 15
Figure 8 Recommended External Components – SPKR2 Output ................................................ 15
Figure 9 Recommended External Components – SPKR1 Output ................................................ 15
Figure 10 Analogue Audio Input Routing ...................................................................................... 16
Figure 11 Recommended External Components – Single-Ended Audio Input Interface .............. 17
Figure 12 CMX7262 Inputs and Outputs ....................................................................................... 19
Figure 13 CMX7262 Using Internal Audio Codec Interfaced With CMX7141 ............................... 20
Figure 14 CMX7262 Interfaced With CMX7141 Using CMX7141’s Audio Codec ........................ 21
Figure 15 Basic C-BUS Transactions ........................................................................................... 23
Figure 16 C-BUS Data-Streaming Operation ................................................................................ 24
Figure 17 FI Loading from Host .................................................................................................... 26
Figure 18 FI Loading from Serial Memory..................................................................................... 27
Figure 19 Input Data Transfer into the CMX7262 ......................................................................... 36
Figure 20 Output Data Transfer from the CMX7262 ..................................................................... 36
Figure 21 TWELP Encoder Operation Flowchart .......................................................................... 40
Figure 22 C-BUS Timings ............................................................................................................. 49
Figure 23 Mechanical Outline of 64-pin VQFN (Q1) ..................................................................... 50
Figure 24 Mechanical Outline of 64-pin LQFP (L9) ....................................................................... 51
Information in this data sheet should not be relied upon for final product design. It is always recommended
that you check for the latest product datasheet version from the CML website: [www.cmlmicro.com].
2013 CML Microsystems Plc
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D/7262_FI-1.x/4
TWELP Vocoder
CMX7262
History
Version
4
Changes
Initial Encoder Delay added:
Section 6.14: (register summary table) updated
Section 8.1: (register details) updated
Section 8.1.13: register description (Initial Encoder Delay $59) added
Section 9.2: Function Images updated
Miscellaneous typographical and editorial changes
Decoder Noise Gate added:
Section 2.1: (block diagram) updated
Section 6.11: (Noise Gate) added
Section 6.14: (register summary table) updated
Section 8.1: (register details) updated
Section 8.1.16: new register description (Noise Gate Configuration $5E)
Section 9.2: Function Images updated
Test Mode added:
Section 6.13 (register summary table) updated
Section 8.1 (register details) updated
Section 8.1.9, new register description (Frequency Control $52) added
Section 8.1.19 (description for VCTRL register) updated to include Test
Mode
Section 9.2, Function Images updated
Miscellaneous typographical and editorial changes
Added advice about connection to the exposed metal pad in Q1 package.
First approved version
Date
30/08/2013
3
17/04/2013
2
06/09/2012
1
26/07/2012
2013 CML Microsystems Plc
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D/7262_FI-1.x/4
PCB设计
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