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®
Analog and Microcontroller
Products
The following document contains information on Spansion analog and microcontroller products. Although the
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will continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Spansion product. Any changes that
have been made are the result of normal document improvements and are noted in the document revision
summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a
revision summary.
Continuity of Ordering Part Numbers
Spansion continues to support existing part numbers beginning with “MB”. To order these products, please use
only the Ordering Part Numbers listed in this document.
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microcontroller products and solutions.
FUJITSU SEMICONDUCTOR
DATA SHEET
DS04–27270–2E
ASSP for Power Management Applications
(General-Purpose DC/DC Converter)
2ch DC/DC converter IC
with synchronous rectification
MB39A138
■
DESCRIPTION
MB39A138 is a 2ch step-down DC/DC converter equipped with a bottom detection comparator and N-ch/
N-ch synchronous rectification. It supports low on-duty operation to allow stable output of low voltages when
there is a large difference between input and output voltages. MB39A138 realizes ultra-rapid response and
high efficiency with built-in enhanced protection features.
■
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High efficiency
High accurate reference voltage
Input voltage range
Output voltage setting range
:
±1.0%
(indoor temperature )
: 6 V to 24 V
: CH1 0.7 V to 5.2 V
: CH2 2.0 V to 5.2 V
Built-in diode for boot strap
Built-in over voltage protection function
Built-in under voltage protection function
Built-in over current detection function
Built-in over temperature protection function
Built-in soft-start circuit without load dependence
Built-in discharge control circuit
Built-in synchronous rectification type output steps for N-ch MOS FET
Standby current
: 0
μA
(Typ)
Small package
: TSSOP-24
■
APPLICATIONS
•
•
•
•
•
Digital TV
Photocopiers
STB
BD, DVD players/recorders
Projectors
Various other advanced devices
Copyright©2009-2011 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2011.3
MB39A138
■
PIN ASSIGNMENT
(TOP VIEW)
CTL1
CS1
FB1
VO1
ILIM1
GND
CVBLPF
CTL2
ILIM2
VO2
FB2
CS2
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CB1
DRVH1
LX1
DRVL1
VCC
VB
PGND
DRVL2
LX2
DRVH2
CB2
TEST
(FPT-24P-M10)
2
DS04–27270–2E
MB39A138
■
PIN DESCRIPTIONS
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin Name
CTL1
CS1
FB1
VO1
ILIM1
GND
CVBLPF
CTL2
ILIM2
VO2
FB2
CS2
TEST
CB2
DRVH2
LX2
DRVL2
PGND
VB
VCC
DRVL1
LX1
DRVH1
CB1
I/O
I
I
I
I
I
⎯
I
I
I
I
I
I
I
⎯
O
⎯
O
⎯
O
I
O
⎯
O
⎯
CH1 control pin.
CH1 start time setting capacitor connection pin.
CH1 feedback pin for DC/DC output voltage.
CH1 input pin for DC/DC output voltage.
CH1 over current detection level setting voltage input pin.
Ground pin.
Control circuit bias input pin.
CH2 control pin.
CH2 over current detection level setting voltage input pin.
CH2 input pin for DC/DC output voltage.
CH2 feedback pin for DC/DC output voltage.
CH2 soft-start time setting capacitor connection pin.
Pin for IC test. Connect to GND in the DC/DC operation.
CH2 connection pin for boot strap capacitor.
CH2 output pin for external high-side FET drive.
CH2 inductor and external high-side FET source connection pin.
CH2 output pin for external low-side FET gate drive.
Ground pin for output circuit.
Output circuit bias output pin.
Power supply pin for reference voltage and control circuit.
CH1 output pin for external low-side FET gate drive.
CH1 inductor and external high-side FET source connection pin.
CH1 output pin for external high-side FET gate drive.
CH1 connection pin for boot strap capacitor.
Description
DS04–27270–2E
3
MB39A138
■
BLOCK DIAGRAM
CTL1 CTL2 VCC
1
8
20
<CH1>
4
/CTL1
UVP,OTP
5
μA
FB1
VO
Control
<Error Comp.>
−
+
+
INTREF1
CS1
2
<ILIM Comp.>
LX1
−
PGND
+
/CTL1,/UVLO
UVP,OTP
−
10
μA
+
VO1 VCC
t
ON
Generator
R
S
CTL
5.2 V Reg.
REF
24
Drv-1
VO1
VB
19 (5.2 V)
CB1
DRVH1
LX1
DRVL1
PGND
3
Q
Drive
Logic
23
22
Drv-2
21
18
ILIM1
bias
5
<OVP Comp.>
+
ovp_q1
−
INTREF1
x 1.15 V
<UVP Comp.>
−
uvp_q1
+
R
50
μs
delay
S
Q
UVLO
7
CVBLPF
R
1.7 ms
delay
S
Q
H:UVLO
release
INTREF1
x 0.7 V
VO2
<CH2>
OTP
10
uvp_q2 ovp_q2
bias
14
CB2
DRVH2
LX2
DRVL2
The configuration of a control circuit is the same as that of CH1.
FB2
11
15
CS2
16
12
17
ILIM2
9
6
GND
4
DS04–27270–2E
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