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Motorola Semiconductor Engineering Bulletin
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Resetting MCUs
By Ross Mitchell
MCU Applications
Motorola Ltd.
East Kilbride, Scotland
Introduction
A simple function such as reset can cause many problems since
different applications impose very different conditions on the start up and
power down of the microcontroller unit (MCU). This document covers the
main issues relating to reset and aims to lead the user of the M68HC05
and M68HC11 devices to a safe a reliable approach for the application.
Reset in its most basic function ensures that the MCU starts executing
code in a controlled manner once power is applied. It may also be used
to prevent the device running out of specification (often in conjunction
with external devices) and can cause a system reset at the board level
whenever the MCU has not executed the code in the expected way
(watchdog).
© Motorola, Inc., 1993, 2000
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Factors which affect reset are:
1. External components attached to the RESET pin
2. Low-voltage reset (LVR) on chip
3. Power-on reset (POR) detection
4. System power-up sequence
5. Watchdog operation
6. Electrically erasable, programmable read-only memory
(EEPROM) on chip
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7. Battery backup
8. Device controls to its own power off
9. Partial power loss
10. HC05 clock source
11. Power applied resets
These factors are explained in detail later in this application note. In most
applications several factors apply and so it may be a combination of
these elements of reset functionality that must be considered for the safe
operation of the MCU application.
Almost all HC05 and HC11 devices have an external 4-MHz or 8-MHz
crystal and so it is assumed that the device will have a stable oscillator
within 10 ms of V
DD
reaching 4 V (5-V V
DD
is also assumed, unless
stated otherwise). Other possibilities for clock sources are discussed in
HC05 Clock Source.
External Components Attached to the RESET Pin
At the simplest level, a battery connection is connected to the V
DD
pin of
the HC05 device and the V
DD
reaches 4.5 V within 1 ms. This assumes
a relatively small reservoir capacitor (for instance, 1
µF).
In this case, the
crystal oscillator will usually start between 5 ms and 10 ms after power
on and the V
DD
supply will be above the minimum allowed for the system
clock. Remember that the 3-V specification normally includes reduced
operating frequency.
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External Components Attached to the RESET Pin
In this case, the internal reset circuit of the HC05 device will hold reset
low internally for the first 4064 system clock cycles (2 ms at 4-MHz
clock). Thus, the internal reset will be released between 7 ms and 12 ms
after power on. This arrangement simply requires a 10-kΩ pullup resistor
externally on the RESET pin. Some HC05 devices have an internal
resistor which means that the RESET pin may be left unconnected or
simply have an external capacitor.
In a situation where the power supply takes more than 10 ms to reach
4 V, the oscillator is likely to have started up and the internal reset
released before the V
DD
pin reaches the minimum voltage for the
particular clock frequency used in the application. This could cause
incorrect device operation and a fatal error for the application is likely. In
this case an external delay is necessary on the RESET pin.
The simplest delay is a resistor/capacitor (RC) network (see
Figure 1)
where the capacitor is charged up by the current flowing through the
resistor until it reaches a level detected by the HC05 RESET pin circuitry
as a logic 1 state. This value is normally defined as a minimum required
V
IH
of 0.7 x V
DD
; however, the actual detection voltage is often much
lower and can be as little as 0.5 x V
DD
(2.5 V with a V
DD
= 5.0 V). The
RESET pin does have a Schmitt input but the hysteresis can be as little
as 300 mV on some devices. The diode ensures that the capacitor
discharges quickly with a sudden fall in V
DD
; otherwise, the capacitor
could keep the MCU powered up for a short time, especially if the MCU
is in stop mode where power consumption is very low.
+5 V
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D1
47 kΩ
MCU
V
DD
SUPPLY
RESET
220 nF
RESET PIN
RESET RELEASED
RESET ACTIVE
Figure 1. RC Network to Delay Reset Release
by Approximately 10 ms
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Ideally there would be no restriction on the values of the resistors and
capacitors, but there are other considerations. Internal leakage currents
for the RESET pin are normally specified at 1
µA
maximum which means
that the resistor has a maximum value of 100 kΩ and the capacitor
should not be an electrolytic type to keep the stop current to a minimum.
Ceramic capacitors are recommended as a compromise between low
cost, low leakage, and good high-frequency response. The RESET pin
capacitance is very low (less than 5 pF).
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There are also limits for the minimum resistor impedance since the
maximum pulldown current is approximately 5 mA at 1 V (V
OL
). Together
with the low-impedance voltage source of the external capacitor, it is
necessary to ensure a minimum pullup resistor value of 2 kΩ. See
Watchdog Operation
for details of the output mode of the RESET pin
where this feature is available on the device.
Low-Voltage Reset (LVR) On Chip
To protect against total or partial loss of power, some devices have an
LVR circuit which effectively resets the device while the V
DD
supply is
lower than the trigger point. It is difficult to make an accurate voltage
reference with high-density complementary metal oxide semiconductor
(HCMOS) designs and so there is often a manufacturing tolerance built
into the specification. As a consequence, the minimum trigger voltage
can be sufficiently low that the device cannot run at the maximum bus
speed for reliable operation before the LVR circuit resets the device.
This restricts the maximum bus speed whenever the LVR circuit is used
to protect the device from runaway.
Significant advantages of the built-in LVR circuit are the reliability of the
integration of the LVR function and low cost. Additionally, the application
can determine the presence of a low-power reset rather than an external
reset. This can be achieved by the use of either separate vectors for the
LVR and normal reset or by means of a register containing a reset
condition status flag. This is of course not normally possible with an
external LVR circuit.
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Power-On Reset (POR) Detection
EEPROM On Chip
discusses protection for on-chip EEPROM where the
use of an external LVR device is highly recommended.
Power-On Reset (POR) Detection
While the LVR circuit can protect against a partial power loss, the POR
function can only indicate a total loss of power followed by power up. The
V
DD
supply must drop to less than 0.2 V to ensure that the POR register
is reset correctly. On power up, a bit in one of the HC05 registers (often
the miscellaneous register if it exists) will be set to a logic high state. This
bit once cleared (by reading the bit) will remain in the logic low state even
if an external reset occurs and only be reset to a 1 when the power is
totally lost and returned.
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System Power-Up Sequence
When power is applied to the system, it will normally take a finite period
to achieve the designed operating voltage. During this time, the MCU
may be required to maintain a specific state on its output pins and hold
off any execution of code until it is safe to commence running the
application.
Once power is applied to an HC05 device, the oscillator will start running
whether reset is held in the active state or not. Of course the oscillator
takes a short time to start up (4-MHz crystals take about 5 ms to start
and 32-kHz crystals take much longer, often as much as 500 ms), but
once the first couple of clocks have occurred, the active state (logic 0) of
the RESET pin normally configures the port lines to be inputs or to a
known state if they are only able to operate in output mode. In this way,
the external circuitry can assume a known state on the MCU pins just a
short time after power on but before the MCU reset is released.
Please remember that the port data registers are not usually initialized
by power on or reset and so a reset will normally leave the port data
unchanged and simply place the port in input mode.
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