S5D0127X01 Data Sheet
MULTISTANDARD VIDEO DECODER/SCALER
The S5D0127X01 converts analog NTSC, PAL or SECAM
video in composite, S-video, or component format to
digitized component video. Output data can be selected for
CCIR 601 or square pixel sample rates in either YCbCr or
RGB formats. The digital video can be scaled down in both
the horizontal and vertical directions. The S5D0127X01
also decodes Intercast, Teletext, Closed Caption, and WSS
data with a built-in bit data slicer. Digitized CVBS data can
be output directly during VBI for external processing.
100 PQFP
MULTIMEDIA VIDEO
FEATURES
• Accepts NTSC-M/N/4.43, PAL-M/N/B/G/H/I/D/K/L and
SECAM formats with auto detection
• 6 analog inputs: 3 S-video, 6 composite, or 1 3-wire
YCbCr component video
• 2-line luma and chroma comb filters including adaptive
luma comb for NTSC
• Programmable luma bandwidth, contrast, brightness,
and edge enhancement
• Programmable chroma bandwidth, hue, and saturation
• High quality horizontal and vertical down scaler
• Intercast, Teletext and Closed Caption decoding with
built-in bit slicer
• Direct output of digitized CVBS during VBI for Intercast
application
• Analog square pixel or CCIR 601 sample rates
• Output in 4:4:4, 4:2:2, or 4:1:1 YCbCr component, or
24-bit or 16-bit RGB formats with dithering
• YCbCr 4:2:2 output can be 8 or 16 bits wide with
embedded timing reference code support for 8-bit mode
• Simultaneous scaled and non-scaled digital output ports
outputs for 8-bit mode.
• Direct access to scaler via bi-directional digital port.
• Programmable Gamma correction table
• Programmable timing signals
• Industry standard IIC interface
• Digital Video
• Video Capture/Editing
ORDERING INFORMATION
Device
S5D0127X01-
Q0R0
Package
100 PQFP
Temperature Range
-20°~+70°C
RELATED PRODUCTS
• S5D0123X01
ENCODER
MULTISTANDARD
VIDEO
APPLICATIONS
• Multimedia
Modified on May/04/2000
ELECTRONICS
PAGE 1 OF 96
BLOCK DIAGRAM
S5D0127X01 Data Sheet
ELECTRONICS
Digital
Input
Timing
Line Lock,
Timing
Generation
HS1
HS2
VS
HAV
VAV
CK
CK2
SCH
PID
Scaler Input OR Simultaneous Non Scaler Output OR 24-bit Output
Non Scaler Output
EHAV
EVAV
EXV[7:0]
Luma
Processing
SRAM
Variable
LPF
Chroma
Processing
Vertical
Scaler
Comb
Filter
Data
Output
Format
Horizontal
Scaler
Y[7:0]
Color
Space
Converter
C[7:0]
Gamma
LUT
Sliced VBI or Raw CVBS
VBI Data
Decoding
OEN
CCEN
CCDAT
XTALI
XTALO
HS1
VS
COMP2
VRT
VRB
Reference
Generator/
Compensation
EXV
Direct.
Control
AY[2:0]
AC[2:0]
6 input MUX
2-AGCs
2-ADCs
Modified on May/04/2000
Gain/Offset
Control
SCLK
SDAT
AEX1,0
IIC Host
Interface
MULTIMEDIA VIDEO
PAGE 2 OF 96
S5D0127X01 Data Sheet
PIN ASSIGNMENT - 100 PQFP
MULTIMEDIA VIDEO
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
HS2(IIC)
SCLK
CCEN
CCDAT
SDAT
EXV7
AEX1
AEX0
EXV6
VDD3
VDD3
VSS
VSS
EXV5
EXV4
EXV3
Y7
Y6
Y5
Y4
NCP
NCP
NCP
VRB
VSS
VDD
PORTA
TESTEN
NCP
NCP
NCP
Y3
Y2
Y1
Y0
C7
VDD3
VDD3
VSS
VSS
C6
C5
C4
C3
C2
NCP
NCP
VAV(OENC0)
EVAV(OENC1)
EHAV
CK2
ODD
VS
SCH(PORTB)
HAV
HS1
C1
C0
NCP
NCP
EXV1
EXV2
NCP
NCP
VRT
VSS
XTALO
XTALI
VDDA1
RST
81 NCP
82 NCP
83 VSS
84 AY0
85 VDDA
86 AY1
87 VSS
88 AY2
89 VDDA
90 AC0
91 VSS
92 AC1
93 VDDA
94 AC2
95 VSS
96 TEST
97 COMP2
98 VDDA
99 NCP
100 NCP
S5D0127X01
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
VDD3
VDD3
VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VSS
OEN
EXV0
PID
CK
VSS
VDD
Modified on May/04/2000
ELECTRONICS
PAGE 3 OF 96
S5D0127X01 Data Sheet
PIN DESCRIPTION
Pin Name
INPUT
AY0
AY1
AY2
AC0
AC1
AC2
XTALI
XTALO
RST
84
86
88
90
92
94
8
7
10
I
I
I
I
I
I
I
O
I
Pin #
Type
Description
MULTIMEDIA VIDEO
1 of 6 analog CVBS or 1of 3 S-video Y inputs.
1 of 6 analog CVBS or 1of 3 S-video Y inputs.
1 of 6 analog CVBS input or 1 of 3 S-video Y inputs or Y input for 3
wire component input
1 of 6 analog CVBS or 1 of 3 S-video C inputs.
1 of 6 analog CVBS or 1 of 3 S-video C inputs or Cb input for 3 wire
component input
1 of 6 analog CVBS or 1 of 3 S-video C inputs or Cr input for 3 wire
component input
Pin 1 for an external crystal or TTL clock input.
Pin 2 for an external crystal.
Chip reset. Active low signal.
OUTPUT (All output pins can be selectively three-stated)
Y0 - Y7, C0 - C7 45-48,53-56,33-
39,44
EXV0 - EXV7
16,27,28,61-63,
68,71
O
I/O
Digital video outputs.
Expanded digital video I/O port. Can be configured as an additional
8-bit output port (no scaling), or additional outputs of the main digital
output stream for 24 bit output modes, as an 8-bit input for direct
digital access of the down scaler.
Programmable horizontal timing signal. One pulse every video line.
When the EXV port is configured as an input, this pin can be
programmed as an input.
Programmable horizontal timing signal. One pulse every video line.
At power up, this pin needs a 10 kΩ pull-down resistor to configure
the chip to operate in IIC mode.
Programmable vertical timing signal. When the EXV port is
configured as an input, this pin can be programmed as an input.
Programmable horizontal active video flag.
Programmable vertical active video flag.
During reset, the pin is an input and the logic state of this pin is
latched into the
OENC[0]
register bit. Use a 10 kΩ resistor for pull-up
or pull-down.
Valid pixel data flag. Polarity is programmable. Active when output
video data is valid.
HS1
26
I/O
HS2(IIC)
76
I/O
VS
HAV
VAV(OENC0)
23
25
3
I/O
O
I/O
EHAV
5
O
Modified on May/04/2000
ELECTRONICS
PAGE 4 OF 96
S5D0127X01 Data Sheet
PIN DESCRIPTION (Continued)
Pin Name
EVAV(OENC1)
4
Pin #
Type
I/O
Description
MULTIMEDIA VIDEO
Valid line flag. Polarity is programmable. Active when output video
line is valid. During reset, the pin is an input and the logic state of
this pin is latched into the
OENC[1]register
bit. Use a 10 kΩ resistor
for pull-up or pull-down.
Odd field flag. Polarity is programmable. Active for fields 1 and 3.
PAL ID flag. High for phase alternating line.
Digital video data, timing and clock output 3-state control.
Pixel clock. In normal decoding mode, this is an output. When the
EXV port is used as an input, this can be programmed as an input
pixel clock.
Pixel output clock (rate is one half of CK) aligned to HAV signal.
Sliced VBI data output. Data can be from Closed Caption, Teletext,
Intercast, or WSS type encoded data.
When high, this pin indicates that valid VBI data is being clocked out
at the CCDAT pin or at the digital video output.
ODD
PID
OEN
CK
22
17
15
18
O
O
I
I/O
CK2
CCDAT
CCEN
21
73
74
O
O
O
MULTI-PURPOSE I/O PORTS AND TEST ENABLE
PORTA
SCH(PORTB)
TESTEN
TEST
58
24
57
96
I/O
I/O
I
I
Multi-purpose I/O port.
Multi-purpose I/O port.
When tied to VDD, the chip is put into the test mode. For normal use,
this pin should be connected to VSS.
When tied to VDD, the chip is put into the test mode. For normal use,
this pin should be connected to VSS.
REFERENCE AND COMPENSATION
VRT
VRB
COMP2
77
78
97
I/O
I/O
I/O
ADC VRT compensation (requires an external 0.1
µ
F capacitor
connected to VSS).
ADC VRB compensation (requires an external 0.1
µ
F capacitor
connected to VSS).
Internal 1.3 V reference (requires an external 0.1
µ
F capacitor
connected to VSS).
HOST INTERFACE
SCLK
SDAT
AEX0 - AEX1
75
72
69 - 70
I
I/O
I
Serial clock for IIC host interface.
Serial data for IIC host interface.
Device ID selection for IIC host interface.
Modified on May/04/2000
ELECTRONICS
PAGE 5 OF 96
测试/测量
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
