IN74HC03A
IN74HC03A
Quad 2-Input NAND Gate
with Open-Drain Outputs
High-Performance Silicon-Gate CMOS
The IN74HC03A is identical in pinout to the LS/ALS03. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LS/ALSTTL outputs.
The IN74HC03A NAND gate has, as its output, a high-performance
MOS N-Channel transistor. This NAND gate can, therefore, with a
suitable pullup resistor, be used in wired-AND applications.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC03AN Plastic
IN74HC03AD SOIC
T
A
= -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
A
L
L
H
PIN 14 =V
CC
PIN 7 = GND
H
B
L
H
L
H
Output
Y
Z
Z
Z
L
Z= High Impedance
Rev. 00
IN74HC03A
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields.
However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this
high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
Rev. 00
IN74HC03A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
Parameter
Test Conditions
V
Guaranteed Limit
25
°C
to
-55°C
1.5
3.15
4.2
0.5
1.35
1.8
0.1
0.1
0.1
0.26
0.26
±0.1
1.0
≤85
°C
1.5
3.15
4.2
0.5
1.35
1.8
0.1
0.1
0.1
0.33
0.33
±1.0
10
≤125
°C
1.5
3.15
4.2
0.5
1.35
1.8
0.1
0.1
0.1
0.4
0.4
±1.0
40
µA
µA
Unit
V
IH
Minimum High-
Level Input Voltage
Maximum Low -
Level Input Voltage
Maximum Low-
Level Output Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢≤
20
µA
V
OUT
=0.1 V or V
CC
-0.1 V
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
⎢I
OUT
⎢ ≤
20
µA
V
IN
=V
IH
⎢I
OUT
⎢ ≤
4.0 mA
⎢I
OUT
⎢ ≤
5.2 mA
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
6.0
6.0
V
V
IL
V
V
OL
V
I
IN
I
CC
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
Maximum Three-
State Leakage
Current
V
IN
=V
CC
or GND
V
IN
=V
CC
or GND
I
OUT
=0µA
Output in High-Impedance
State
V
IN
= V
IL
or V
IH
I
OUT
= V
CC
or GND
I
OZ
6.0
±0.5
±5.0
±10
µA
Rev. 00
IN74HC03A
AC ELECTRICAL CHARACTERISTICS (CL=50pF,Input tr=tf=6.0 ns)
V
CC
Symbol
Parameter
V
Guaranteed Limit
25
°C
to
-55°C
120
24
20
75
15
13
10
10
≤85°C
≤125°C
Unit
t
PLZ
, t
PZL
Maximum Propagation Delay, Input A or B to
Output Y (Figures 1 and 2)
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
Maximum Input Capacitance
Maximum Three-State Output Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per Gate)
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
2.0
4.5
6.0
2.0
4.5
6.0
-
-
150
30
26
95
19
16
10
10
180
36
31
110
22
19
10
10
ns
t
THL
ns
C
IN
C
OUT
pF
pF
Typical @25°C,V
CC
=5.0 V
8.0
pF
C
PD
.Figure 1. Switching Waveforms
Figure 2. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
*
Denotes open-drain outputs
Rev. 00
IN74HC03A
N SUFFIX PLASTIC DIP
(MS - 001AA)
A
14
8
B
1
7
Dimension, mm
Symbol
A
B
C
MIN
18.67
6.1
MAX
19.69
7.11
5.33
0.36
1.14
2.54
7.62
0°
2.92
7.62
0.2
0.38
10°
3.81
8.26
0.36
0.56
1.78
F
L
D
F
C
-T-
SEATING
N
G
D
0.25 (0.010) M T
K
PLANE
G
H
H
J
M
J
K
L
M
N
NOTES:
1. Dimensions “A”, “B” do not include mold flash or protrusions.
Maximum mold flash or protrusions 0.25 mm (0.010) per side.
D SUFFIX SOIC
(MS - 012AB)
Dimension, mm
8
A
14
Symbol
A
MIN
8.55
3.8
1.35
0.33
0.4
1.27
5.27
0°
0.1
0.19
5.8
0.25
MAX
8.75
4
1.75
0.51
1.27
H
B
P
B
C
1
G
7
C
R x 45
D
F
G
-T-
D
0.25 (0.010) M T C M
K
SEATING
PLANE
H
J
F
M
J
K
M
P
R
8°
0.25
0.25
6.2
0.5
NOTES:
1. Dimensions A and B do not include mold flash or protrusion.
2. Maximum mold flash or protrusion 0.15 mm (0.006) per side
for A; for B
‑
0.25 mm (0.010) per side.
Rev. 00
嵌入式系统
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