IN16C1058
OCTAL UART WITH 256-BYTE FIFO
JUNE 2009
REV 1.0
Octal-UART Controller
with 256-Byte FIFO
IN16C1058
Revision 1.0
IK Semicon Co., Ltd.
1
IN16C1058
OCTAL UART WITH 256-BYTE FIFO
JUNE 2009
REV 1.0
CONTENTS
1. Description
............................................................................................................................................... 5
2. Features
.................................................................................................................................................... 5
3. Ordering Information
............................................................................................................................... 6
4. Block Diagram..........................................................................................................................................
7
5. Pin Configuration.....................................................................................................................................
8
5.1 Pin Configuration for 128-Pin TQFP (20x20) Package
................................................................ 8
5.2 Pin Description
............................................................................................................................... 9
Modem and Serial I/O Interface .................................................................................................... 10
Multiport I/O Interfaces .................................................................................................................. 12
Multiport I/O Interfaces .................................................................................................................. 13
Other Interfaces ............................................................................................................................ 13
6. Functional Description
.......................................................................................................................... 14
6.1 Normal mode and MIO mode
....................................................................................................... 14
6.2 MIO mode
...................................................................................................................................... 15
6.3 FIFO Operation
............................................................................................................................. 17
6.4 Hardware Flow Control
................................................................................................................ 17
6.4.1 Auto-RTS .............................................................................................................................. 17
6.4.2 Auto-CTS .............................................................................................................................. 18
6.5 Software Flow Control
................................................................................................................. 19
6.5.1 Transmit Software Flow Control ........................................................................................... 20
6.5.2 Receive Software Flow Control ............................................................................................ 20
6.5.3 Xon Any Function ................................................................................................................. 23
6.5.4 Xoff Re-transmit Function .................................................................................................... 23
6.6 Interrupts
....................................................................................................................................... 24
6.7 DMA Operation
............................................................................................................................. 25
6.7.1 Single DMA transfer (DMA Mode 0/FIFO Disable) .............................................................. 25
6.7.2 Block DMA transfer (DMA Mode 1) ...................................................................................... 26
6.8 Sleep Mode with Auto Wake-Up
.................................................................................................. 26
6.9 Programmable Baud Rate Generator
......................................................................................... 27
6.9 Break and Time-out Conditions
.................................................................................................. 29
7. UART Register Descriptions
................................................................................................................ 30
7.1 Transmit Holding Register (THR, Page 0)
.................................................................................. 34
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IN16C1058
OCTAL UART WITH 256-BYTE FIFO
JUNE 2009
REV 1.0
7.2 Receive Buffer Register (RBR, Page 0)
...................................................................................... 34
7.3 Interrupt Enable Register (IER, Page 0)
..................................................................................... 35
7.4 Interrupt Status Register (ISR, Page 0)
...................................................................................... 36
7.5 FIFO Control Register (FCR, Page 0)
......................................................................................... 37
7.6 Line Control Register (LCR, Page 0)
.......................................................................................... 38
7.7 Modem Control Register (MCR, Page 0)
.................................................................................... 39
7.8 Line Status Register (LSR, Page 0)
............................................................................................ 40
7.9 Modem Status Register (MSR, Page 0)
...................................................................................... 41
7.10 Scratch Pad Register (SPR, Page 0)
......................................................................................... 41
7.11 Divisor Latches (DLL, DLM, Page 1)
......................................................................................... 41
7.12 Global Interrupt Control Register (GICR, Page 2)
................................................................... 42
7.13 Global Interrupt Status Register (GISR, Page 2)
..................................................................... 43
7.14 Transmit FIFO Count Register (TCR, Page 2)
.......................................................................... 43
7.15 Receive FIFO Count Register (RCR, Page 2)
........................................................................... 44
7.16 Flow Control Status Register (FSR, Page 2)
............................................................................ 44
7.17 Page Select Register (PSR, Page 3)
......................................................................................... 45
7.18 Auto Toggle Control Register (ATR, Page 3)
........................................................................... 46
7.19 Enhanced Feature Register (EFR, Page 3)
.............................................................................. 47
7.23 Additional Feature Register (AFR, Page 4)
.............................................................................. 48
7.24 Xoff Re-transmit Count Register (XRCR, Page 4)
................................................................... 48
7.25 Transmit FIFO Trigger Level Register (TTR, Page 4)
.............................................................. 49
7.26 Receive FIFO Trigger Level Register (RTR, Page 4)
............................................................... 49
7.27 Flow Control Upper Threshold Register (FUR, Page 4)
......................................................... 49
7.28 Flow Control Lower Threshold Register (FLR, Page 4)
.......................................................... 49
8. Option Register Descriptions
............................................................................................................... 51
8.1 Option Registers Map
.................................................................................................................. 51
8.2 Device Information Register........................................................................................................
52
8.3 Interface Information Register
.................................................................................................... 53
8.4 Interrupt Mask Register
............................................................................................................... 53
8.5 Interrupt Poll Register
.................................................................................................................. 54
9. Programmer’s Guide
............................................................................................................................. 55
10. Electrical Characteristics
.................................................................................................................... 60
10.1 Absolute Maximum Ratings
...................................................................................................... 60
10.2 Power Consumption
.................................................................................................................. 60
10.3 DC Electrical Characteristics
.................................................................................................... 60
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IN16C1058
OCTAL UART WITH 256-BYTE FIFO
JUNE 2009
REV 1.0
10.4 AC Electrical Characteristics
.................................................................................................... 61
11.Package Outline
.................................................................................................................................... 66
4
IN16C1058
OCTAL UART WITH 256-BYTE FIFO
JUNE 2009
REV 1.0
1. Description
IN16C1058 is a octal UART(Universal Asynchronous Receiver/Transmitter) with 256-byte
FIFO supporting maximum communication speed of 5.3Mbps. It offers flow control
function by hardware or software and signal lines which can open or close the Tx/Rx
input/output when communicating by RS-422 or RS-485. It can handle eight internal
interrupt signals (INT0, INT1, INT2, INT3, INT4, INT5, INT6 and INT7) with one global
interrupt signal line (INT) and offers a new ‘Xoff re-transmit’ function in addition to Xon
any character.
UART can convert 8-bit parallel data to asynchronous serial data and vice versa. It can
transmit 5 to 8-bit letters, program I/O interrupt trigger level and has 256-byte I/O data
FIFO.
UART can generate any baud rate using clock and programmable divisor, transmit data
with even, odd or no parity and 1, 1.5, 2 stop bit, and detect break, idle, framing error,
FIFO overflow and parity error in input data.
UART has a software interface for modem controlling.
IN16C1058 offers TQFP128 (20x20 body) packages.
2. Features
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8 Channel UART
3.3V Operation with 5V tolerant Inputs
Up to 5.3 Mbps Baud Rate (Up to 85 MHz Oscillator Input Clock)
256-byte Transmit FIFO
256-byte Receive FIFO with Error Flags
Industrial Temperature Range (-40
℃
to +85
℃
)
Programmable and Selectable Transmit and Receive FIFO Trigger Levels for DMA
and Interrupt Generation
Software (Xon/Xoff) / Hardware (nRTS/nCTS) Flow Control
- Programmable Xon/Xoff Characters
- Programmable Auto-RTS and Auto-CTS
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Global Interrupt Mask/Poll Control
Optional Data Flow Resume by Xon Any Character Control
Optional Data Flow Additional Halt by Xoff Re-transmit Control
Dedicated pins for automatic bus control of RS-422 and RS-485 communications.
- RS-422 Point to Point/Multi-Drop Control
- RS-485 Echo/Non Echo Control
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DMA Signaling Capability for Both Received and Transmitted Data
Software Selectable Baud Rate Generator
Prescaler Provides Additional Divide-by-4 Function
Fast Data Bus Access Time
Programmable Sleep Mode
Programmable Serial Interface Characteristics
5
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