16Mx64 bit SDRAM SO DIMM X-Series
PC/100 SDRAM Specification Supporting
based on 16Mx16 SDRAM, LVTTL, 4-Banks & 8K-Refresh
HYM72V65M1631
PRELIMINARY
DESCRIPTION
The HYM72V65M1631 X-Series are high speed 3.3-Volt Synchronous DRAM Modules composed of four
16Mx16 bit Synchronous DRAMs in 54-pin TSOPII and 8-pin TSSOP 2K bit E
2
PROM on a 144-pin Zig Zag
Dual pin glass-epoxy printed circuit board. Three 0.1uF decoupling capacitors per each SDRAM are
mounted on the module.
The HYM72V65M1631 X-Series are gold plated socket type Dual In-line Memory Modules suitable for
easy interchange and addition of 128M bytes memory. All inputs and outputs are synchronized with the
rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth.
FEATURES
•
•
•
•
•
•
•
•
1.00”(31.75mm) PCB Height
One Row of SDRAMs on SO DIMM
144-Pin Unbuffered SO DIMM
Serial Presence Detect with Serial E
2
PROM
Meets all the other JEDEC specifications
Single 3.3V±0.3V power supply
All device pins are LVTTL compatible
8192 refresh cycles every 64ms
•
All inputs and outputs referenced to positive
edge of system clock
•
Internal four banks operation
•
Programmable Burst Length and Burst Type
- 1,2,4,8 and Full page for Sequential Burst
- 1,2,4 and 8 for Interleave Burst
•
Programmable /CAS latency ; 2,3 clocks
•
Data mask function by DQM
ORDERING INFORMATION
Part No.
HYM72V65M1631TX-8
HYM72V65M1631TX-10P
HYM72V65M1631TX-10S
HYM72V65M1631LTX-8
HYM72V65M1631LTX-10P
HYM72V65M1631LTX-10S
Clock
Frequency
Power
PCB
Height
Package
Based Comp. Part No
HY57V2571620TC-8
HY57V2571620TC-10P
HY57V2571620TC-10S
HY57V2571620LTC-8
HY57V2571620TLC-10P
HY57V2571620LTC-10S
125MHz
100MHz
100MHz
125MHz
100MHz
100MHz
Normal
1.00”
Low
Power
TSOPII
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.0 / Dec.98
HYM72V65M1631 X-Series
PIN DESCRIPTION
Pin
CK0, CK1
CKE0
/S0
Pin Name
Clock
Clock Enable
Chip Select
Row Address
Strobe, Column
Address
Strobe,
Write
Enable
Data Input
Output Mask
Data Input
Output
Bank Address
Address
Power
Supply/Ground
Serial Address
and Data Input /
Output.
Serial Clock
INPUT
Write Protection
/
/
Description
The system clock input; All other inputs are registered to the SDRAM on the rising
edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be either
one of the states among power down, suspend, or self refresh.
Command input enable of mask except CLK, CKE and DQM
/RAS,
/CAS,/WE
/RAS, /CAS and /WE define the operation.
Refer function truth table for details
DQM0-7
DQ0-DQ63
BA0, BA1
A0-A12
Vcc/Vss
SDA
SCL
SA0-SA2
WP
DQM control output buffer in read mode and masks input data in write mode
Multiplexed data input / output pin
Select either one of banks during both /RAS and /CAS activity
Row Address : RA0 ~ RA12, Column Address : CA0 ~ CA8
Auto-precharge flag: A10
Power supply and ground for internal circuit and input buffer
Serial Address and Data Input / Output for EEPROM
Serial Clock
Addresses in Serial E
2
PROM for Socket Presence.
EEPROM Write Protection
Rev. 0.0/Dec.98
2
HYM72V65M1631 X-Series
PIN NAME
#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
NAME
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
Vss
DQM0
DQM1
Vcc
A0
A1
A2
Vss
DQ8
DQ9
DQ10
DQ11
Vcc
DQ12
DQ13
DQ14
DQ15
Vss
NC
NC
CK0
Vcc
/RAS
/WE
/S0
NC
#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
NAME
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
Vss
DQM4
DQM5
Vcc
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
Vcc
DQ44
DQ45
DQ46
DQ47
Vss
NC
NC
CKE0
Vcc
/CAS
NC
A12
NC
#
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
NAME
NC
Vss
NC
NC
Vcc
DQ16
DQ17
DQ18
DQ19
Vss
DQ20
DQ21
DQ22
DQ23
Vcc
A6
A8
Vss
A9
A10(AP)
Vcc
DQM2
DQM3
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
SDA
Vcc
#
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
NAME
*CK1
Vss
NC
NC
Vcc
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
DQ54
DQ55
Vcc
A7
BA0
Vss
BA1
A11
Vcc
DQM6
DQM7
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
SCL
Vcc
Note : *CK1 is connected with termination R/C.(Refer to the Block Diagram.)
3
Rev. 0.0/Dec.98
HYM72V65M1631 X-Series
BLOCK DIAGRAM
Note :
1. The padding capacitance of termination R/C for CK1 is 10pF.
2. Three 0.1uF decoupling capacitors per SDRAM device.
Rev. 0.0/Dec.98
4
HYM72V65M1631 X-Series
SERIAL PRESENCE DETECT
BYTE
NUMBER
BYTE0
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
BYTE10
BYTE11
BYTE12
BYTE13
BYTE14
BYTE15
BYTE16
BYTE17
BYTE18
BYTE19
BYTE20
BYTE21
BYTE22
BYTE23
BYTE24
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
BYTE31
BYTE32
BYTE33
BYTE34
BYTE35
BYTE36 -
61
BYTE62
BYTE63
BYTE64
BYTE65 -
71
BYTE72
FUNCTION
DESCRIBED
# of Bytes Written into Serial Memory
at Module Manufacturer
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
Data Width of This Assembly (Continued)
Voltage Interface Standard of This Assembly
SDRAM Cycle Time @ /CAS Latency=3
Access Time from Clock @ /CAS Latency=3
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Width
Error Checking SDRAM Width
Minimum Clock Delay Back to Back Random Column
Address
Burst Lengths Supported
# of Banks on SDRAM Device
CAS # Latency
CS # Latency
Write Latency
SDRAM Module Attributes
SDRAM Module Attributes, General
SDRAM Cycle Time @ /CAS Latency=2
Access Time from Clock @ /CAS Latency=2
SDRAM Cycle Time @ /CAS Latency=1
Access Time from Clock @ /CAS Latency=1
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active Delay (tRRD)
Minimum /RAS to /CAS Delay (tRCD)
Minimum /RAS Pulse width (tRAS)
Module Bank Density
Command & Address signal input setup time (tAS)
Command & Address signal input hold time (tAH)
Data signal input setup time (tDS)
Data signal input hold time (tDH)
Superset Information(May be used in the future)
SPD Revision
Checksum for Byte 0-62
Manufacturer JEDEC ID Code
Manufacturer JEDEC ID Code
-
2ns
1ns
2ns
1ns
8ns
6ns
FUNCTION
-8
-10P
128 Bytes
256 Bytes
SDRAM
13
9
1 Banks
64 Bits
-
LVTTL
10ns
6ns
None
7.8125µs
/ Self Refresh Supported
X16
None
tCCD=1 Latency
1,2,4,8,Full Page
4 Banks
/CAS Latency=2,3
/CS Latency=0
/WE Latency=0
Neither Buffered nor Registered
+/-10% voltage tolerance, Burst
read, Single bit write, Precharge
all, Auto precharge
10ns
6ns
-
-
20ns
16ns
20ns
48ns
10ns
6ns
-
-
20ns
20ns
20ns
50ns
128MB
2ns
1ns
2ns
1ns
-
Intel SPD 1.2A
-
Hyundai JEDEC ID
Unused
HEI (Korea)
HEA (United States)
HEU (Europe)
-
FAh
2ns
1ns
2ns
1ns
20h
10h
20h
10h
12ns
6ns
-
-
20ns
20ns
20ns
50ns
A0h
60h
00h
00h
14h
10h
14h
30h
10ns
6ns
80h
60h
-10S
-8
VALUE
-10P
80h
08h
04h
0Dh
09h
02h
40h
00h
01h
A0h
60h
00h
82h
10h
00h
01h
8Fh
04h
06h
01h
01h
00h
0Eh
A0h
60h
00h
00h
14h
14h
14h
32h
20h
20h
10h
20h
10h
00h
12h
20h
ADh
FFh
01h
02h
03h
40h
4, 5
20h
10h
20h
10h
C0h
60h
00h
00h
14h
14h
14h
32h
2
A0h
60h
1
-10S
NOTE
Manufacturing Location
5
Rev. 0.0/Dec.98
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