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HS1-3182-9+

产品描述LINE DRIVER, CDIP16
产品类别半导体    模拟混合信号IC   
文件大小261KB,共7页
制造商Intersil ( Renesas )
官网地址http://www.intersil.com/cda/home/
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HS1-3182-9+概述

LINE DRIVER, CDIP16

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DATASHEET
HS-3182
ARINC 429 Bus Interface Line Driver Circuit
The HS-3182 is a monolithic dielectric ally isolated bipolar
differential line driver designed to meet the specifications of
ARINC 429. This device is intended to be used with a
companion chip, HS-3282 CMOS ARINC Bus Interface
Circuit, which provides the data formatting and processor
interface function.
All logic inputs are TTL and CMOS compatible. In addition to
the DATA (A) and DATA (B) inputs, there are also inputs for
CLOCK and SYNC signals which are AND’d with the DATA
inputs. This feature enhances system performance and
allows the HS-3182 to be used with devices other than the
HS-3182.
Three power supplies are necessary to operate the HS-3182:
+V = +15V ±10%, -V = -15V ±10%, and V1 = 5V ±5%. V
REF
is
used to program the differential output voltage swing such that
V
OUT
(DIFF) = ±2VREF. Typically, V
REF
= V1 = 5V ±5%, but a
separate power supply may be used for VREF which should
not exceed 6V.
The driver output impedance is 75 ±20% at +25°C. Driver
output rise and fall times are independently programmed
through the use of two external capacitors connected to the CA
and CB inputs. Typical capacitor values are CA = CB = 75pF for
high-speed operation (100kBPS), and CA = CB = 300pF for
low-speed operation (12kBPS to 14.5kBPS). The outputs are
protected against overvoltage and short circuit as shown in the
Block Diagram. The HS-3182 is designed to operate over an
ambient temperature range of -55°C to +125°C, or -40°C to
+85°C.
TABLE 1. TRUTH TABLE
SYNC CLK DATA (A) DATA (B) A
OUT
X
L
H
H
H
H
L
X
H
H
H
H
X
X
L
L
H
H
X
X
L
H
L
H
0V
0V
0V
B
OUT
0V
0V
0V
COMMENTS
Null
Null
Null
Low
SYNC
FN2963
Rev 3.00
May 30, 2008
Features
• RoHS/Pb-free Available for SBDIP Package (100% Gold
Termination Finish)
• TTL and CMOS Compatible Inputs
• Adjustable Rise and Fall Times via Two External
Capacitors
• Programmable Output Differential Voltage via V
REF
Input
• Operates at Data Rates Up to 100k Bits/s
• Output Short Circuit Proof and Contains Overvoltage
Protection
• Outputs are Inhibited (0V) If DATA (A) and DATA (B)
Inputs are Both in the “Logic One” State
• DATA (A) and DATA (B) Signals are “AND’d” with Clock
and Sync Signals
• Full Military Temperature Range
Pinouts
HS-3182
(16 LD SBDIP)
TOP VIEW
V
REF
1
GND 2
SYNC 3
DATA (A) 4
C
A
5
A
OUT
6
-V 7
GND 8
16 V
1
15 NC
14 CLK
13 DATA (B)
12 C
B
11 B
OUT
10 NC
9 +V
-V
REF
+V
REF
+V
REF
-V
REF
0V
0V
HS-3182
(28 LD CLCC)
TOP VIEW
GND
NC
VREF
NC
NC
25 CLK
24 NC
23 DATA (B)
22 CB
21 NC
20 NC
19 NC
12 13 14 15 16 17 18
AOUT
BOUT
GND
NC
NC
-V
+V
High
Null
NC
DATA (A)
NC
NC
CA
5
6
7
8
9
4
3
2
1
NC 10
NC 11
FN2963 Rev 3.00
May 30, 2008
V1
28 27 26
Page 1 of 7
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