II
CD4049A, CD4050A Typ
s
COS/MOS Hex Buffer/Converters
CD4049A-lnverting Type
CD4050A-Non-lnverting Type
The CD4049A and CD4050A are inverting
and non-inverting hex buffers, respectively,
and feature logic-level conversion using o.nly
one supply voltage (VCC)- The input-signal
high level (V I H) can exceed the V CC supply
voltage when these devices are used for logic-
level conversions_ These devices are intended
for use as COS/MOS to DTL/TTL converters
and can drive directly two DTL/TTL loads_
(VCC=5 V, VOL
~0.4
V, and IDN
~3.2
mA.)
The CD4049A and CD4050A are designated
as replacements for CD4009A and CD4010A,
respectively. Because the CD4049A and
CD4050A require only one power supply,
they are preferred over the CD4009A and
CD4010A and should be used in place of the
CD4009A and CD4010A in all inverter, cur-
rent driver, or logic-level conversion appli-
cations. In these applications the CD4049A
and CD4050A are pin compatible with the
CD4009A and CD4010A respectively, and
can be substituted for these devices in
existing as well as in new designs. Terminal
No. 16 is not connected internally on the
CD4049A or CD4050A, therefore, connection
to this terminal is of no consequence to cir-
cuit operation. For applications not re-
quiring high sink-current or voltage conver-
sion, the CD4069 Hex Inverter is recom-
mended.
These types are supplied in 16-lead hermellc
dual-in-Ilne ceramic packages (D and F
suffixes), 16-lead dual-In-Iine plastic pack-
age
(E
suffix),
U~~lead
ceramic flat packages_-
(K
SUffiX), and In chip form
(H
suffiX).
RECOMMENDED OPERATING CONDITIONS at TA=25
0
C, Except as Noted.
For maximum reliability, nominal operating conditions should be selected so that
operation
IS
always Within the following ranges:
CHARACTERISTIC
Supply·Voltage Range (Vee) (Fo' T A=Fuli Package·
TemperatUie Range)
Input Voltage Range (VI)
IOW·IO·hlgh·level. therefore.t.s recommendf'd that V f ;;;, V CC
LIMITS
Max.
Min.
UNITS
V
V
3
VCC
12
12
'The CD4049 and CD4050 have hlgh·to·low·level voltage conversion capability but not
STATIC ELECTRICAL CHARACTERISTICS
Quiescent
Device
Current,
IL Max.
V
1.5 Min.; 2.25 Typ.
3 Min.; 4.5 Typ.
~~
Features:
•
•
•
•
High sink current for driving
2
TTL loads
High-to-Iow level logic conversion
Quiescent current specified to 15
V
Maximum input leakage of 1 J.LA at 15
V
(full package-temperature range)
3 Min.; 4.5 Typ.
V
7.2
10
2 Min.; 3 Typ.
Applications:
• COS/MOS to DTL/TTL hex converter
• COS/MOS current "sink" or "source"
driver
• COSIMOS high-to-Iow logic-level
converter
~
~
e
~
~
~
~
vee _1_
F
Vss _8_
Gli
HoB
Ioe
Jo[j
e~
e~
~
GoA
"oe
V
I-e
JoD
'oE
LoF
KaE
LoF
F~
vee _1_
VSS _8_
NC'13
~
~
mA
Ne 013
Ne -16
CD4049A
Ne -16
CD4050A
Any Input
15
±10-5 Typ., ±1 Max.
J.LA
Fig.
1 -
Functional diagrams.
554
CD4049A, CD4050A Typ
MA)UMUM RATINGS,
Absolute·Maxlmum Values
STOnAGE·TEMPERATURE RANGE ITstgl
OPEnATING·TEMPERATURE RANGE (TAl
TYPES D. F. H
PACKAGE TYPE E
DCSUPPLY·VOLTAGE RANGE. (VCCl
(Voltages referenced to VSS Termlnall
POWER DISSIPATION PER PACKAGE IP D )
FOR T A= -40 to +60o C (PACKAGE TYPE E)
FOR T A
=
+60 to +85 C (PACKAGE TYPE E )
FOR T A = -55 to +100°C (PACKAGE TYPES D. F)
0
s
P.~CKAGE
-55 to +l25 o C
-40 t(1 +85
0
C
-0.5
tJ
+15
V
!;OOmW
Derate Linearly at 1'2
mW/oC
to 200 mW
'500
mW
I
2
INPUT VOLTAGE
Derate LInearly at 12
mW/oC
to :'00 mW
FOR T A = +100 to +125
0
C IPACKAGE TYPES D. F)
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A = FULL PACKAGE TEMPERATURE RANGE (ALL ?ACKAGE TYPES)
100 mW
INPUT VOL TAGE RANGE. ALL INPUTS
LEAD TEMPERATURE lOURING SOLDERING)
jI,t d,stance
1/16
±
1/32
Inch (I 59
±
079 mm) from case fOlIOs max
-05 to V DO +05
V
e"I'-V
3
Fig. 2-Mintmum and maximum voltage
transfer characteristics for
CD4049A.
INPUT VOLTAOE C
"I
,-y
INPUT vOLTAGE CY1'-V
Fig. 3-Minimum and maximum voltage
transfer characteristics for
CD4050A.
Fig. 4-Mlntmum and maximum voltage
transfer characteristics for
CD4049A.
Fig. 5-Minimum and maximum voltage
transfer characteristics for
CD4050A.
INPUT VOLTAGE
(VI , -
y
'NPUT VOLTAGE (VI
)-y
WlCS-tO."
,acl-IC.'.
Fig.
8-
Typical and minimum n-channel drain
characteristics as
a
function of gate·to·
source voltage
(V
GS) for CD4049A, CD4050A.
Fig.
6-
Typical voltaga transfer charac·
taristics as
a
function of tempera·
ture for CD4049A.
Fig.
7-
TYPical voltage transfer chllrac·
teristics as
a
function of tempera·
ture for CD4050A.
9lCSlO486R.
Fig.
9-
Typical and mintmum p-channel drain
characteristics as
a
function of gate· to·
source voltage
(V
GSJ for CD4049A,
CD4050A.
40
60
BO
100
LOAD CAPACITANCE (CL'-pF'
40
LOAD CAPACITAHU ICL)-P'
Fig.
1()-
Typical high·to·low level propallatlon delay
time vs. CL for CD4049A.
Fig.
11-
Typical high·to·low level propagation delay
time vs.
C
L for CD4050A.
555
CD4049A, CD4050A Typ
s
DYNAMIC ELECTRICAL CHARACTERISTICS at T A=25
0
C; Input t,.tt=20 ns.
CL =15 pF. Re200
kn
CHARACTERISTIC
CONDITIONS
VCC
Propagation Delay Time:
Low-to-High. tpLH
CD4049A
CD4050A
High-to-Low. tPHL
CD4049A
CD4050A
Transition Time:
Low-to-High. tTLH
High-to-Low. tTHL
Input Capacitance. CI
CD4049A
CD4050A
5
10
5
10
5
10
5
10
50
30
20
16
15
5
100
60
45
40
ns
5
10
5
10
5
10
5
10
15
10
55
25
55
30
110
55
ns
5
10
5
10
5
10
5
10
50
25
75
35
80
55
140
85
ns
LIMITS
ALL PKGS.
Typ. Max.
UNITS
Fig.
12-
Typicallow·to-high level propagation delay
time vs. CL for CD4049A.
pF
t.CS·I04 ..
Fig.
13-
Typicallow·to-high level propagation delay
time vs. CL for CD4050A.
LOAD CAPAC.TANCE (CL
ucs-tos:.
1-.'
'00
Fig_
14-
Typical hi/l!-to-Iow level trensition time
vs_ CL for CD4049A, CD4050A.
Fig.
15-
Typicallow·to·high level transition time
vs. CL for CD4049A. CD4050A.
il
~~.
~
'0
~
'0
AMBIENT TEMPERATURE (T A' • 'ULL
'KG
Tit. . RaNGr.
ct
of
•
'101
I
...
~'YT
~"I-""
\~~.\oO.i:7
~
...0I-'
~
.0'
i
z
10 2
~'
\I)~"
...
,CP.
...
~
,o...m::;t:
..
~9'1'-.
III
,:,t,;
1<,0
...
~'I'
."
:s'. .
0'"
01-'
l,.'UT FREOUENCY
Ct.'
'It.
Uti
I
...
/0
92CI-IO$17
Fig.
16-
TypiclIl dissipetion charBCteristics for
CD4049A, CD4050A.
~fJ~·"
1<,'
II
in
i
INPUT IIIIIS! AND "LL TIM[ II, " , '
92es-t()4tolt
'0
tJ7-'
""
~~o
.....f$'
,III
.
'0
INPUT RISE AND 'Al.l TIM[
Itt
,t,
1
IN
Flg_
17-
Typical power dissipation vs_ transition
time per inverter CD4049A.
Fig.
18-
Typical power dissipation
VI.
transition
time per inverter CD4050A.
Yoo
tol
t
bl
IICI·".OI
Fig. 19-Noise,immunity test circUit.
Fig. 20-.,Jnput leakage current test circuit.
Fig.
21
~uiescent
device current test circuit.
Fig.
22 -
(a)Schematic diagram of C04049A,
1
6 identical units.
(b) Schematic diagram of C04050A, 1
6 identical units.
0_
I
556 ____________________________________________________________________
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
