Freescale Semiconductor
Technical Data
DSP56374
Rev. 1, 11/2004
Overview
The DSP56374 is a high density CMOS device with 3.3 V inputs and outputs.
NOTE
This document contains information on a new product.
Specifications and information herein are subject to
change without notice.
Finalized specifications may be published after further characterization and device
qualifications are completed.
The DSP56374 supports digital audio applications requiring sound field processing,
acoustic equalization, and other digital audio algorithms. The DSP56374 uses the high
performance, single-clock-per-cycle DSP56300 core family of programmable CMOS digital
signal processors (DSPs) combined with the audio signal processing capability of the
Freescale Semiconductor, Inc. (formerly Motorola) Symphony™ DSP family, as shown in
Figure 1.
Significant architectural enhancements include a barrel shifter, 24-bit addressing,
and direct memory access (DMA). The DSP56374 offers 150 million instructions per second
(MIPS) using an internal 150 MHz clock.
Table of Contents
Section
Page
1 Features........................................ 2
2 Documentation.............................. 4
3 Signal Groupings .......................... 4
4 Maximum Ratings ....................... 24
5 Power Requirements................... 25
6 Thermal Characteristics.............. 26
7 DC Electrical Characteristics ...... 26
8 AC Electrical Characteristics....... 27
9 Internal Clocks ............................ 27
10 External Clock Operation .......... 29
11 Reset, Stop, Mode Select, and
Interrupt Timing ........................... 30
12 Serial Host Interface SPI Protocol
Timing.......................................... 34
13 Serial Host Interface (SHI) I2C
Protocol Timing ........................... 40
14 Programming the Serial Clock .. 42
15 Enhanced Serial Audio Interface
Timing.......................................... 43
16 Timer Timing ............................. 48
17 GPIO Timing ............................. 48
18 JTAG Timing ............................. 50
19 Watchdog Timer Timing ............ 52
Appendix A Package Information. 53
Appendix B IBIS Model ................. 63
Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR
“asserted”
Used to indicate a signal that is active when pulled low (For
example, the RESET pin is active when low.)
Means that a high true (active high) signal is high or that a low true
(active low) signal is low
“deasserted” Means that a high true (active high) signal is low or that a low true
(active low) signal is high
Examples:
Signal/
Symbol
PIN
PIN
PIN
PIN
Logic State
True
False
True
False
Signal State
Asserted
Deasserted
Asserted
Deasserted
Voltage*
V
IL
/ V
OL
V
IH
/ V
OH
V
IH
/ V
OH
V
IL
/ V
OL
Note:
*Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
PRELIMINARY
Features
5
15*
12
12*
3
Memory Expansion Area
SHI
Interface
GPIO
ESAI
Interface
ESAI_1
Interface
Triple
Timer
Watch
dog
Timer
Program
RAM
6k
×
24
ROM
20k
×
24
X Data
RAM
6k
×
24
ROM
4k
×
24
XM_EB
Y Data
RAM
6k
×
24
ROM
4k
×
24
YM_EB
PIO_EB
PM_EB
DDB
YDB
XDB
PDB
GDB
Peripheral
Expansion Area
Address
Generation
Unit
Six Channel
DMA Unit
YAB
XAB
PAB
DAB
24-Bit
Bootstrap
ROM
DSP56300
Core
Internal
Data
Bus
Switch
Clock
Gen.
Power
Mgmt.
PLL
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Data ALU
24
×
24+56
→
56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
4
JTAG
OnCE
XTAL
EXTAL
RESET
PINIT/NMI
MODA/IRQA/GPIO
MODB/IRQB/GPIO
MODC/IRQC/GPIO
MODD/IRQD/GPIO
* ESAI_1 and dedicated GPIO pins are not available in the 52-pin package.
Figure 1.
DSP56374 Block Diagram
1
1.1
•
•
•
•
•
•
•
•
•
•
2
Features
DSP56300 Modular Chassis
150 Million Instructions Per Second (MIPS) with a 150 MHz clock at an internal logic supply (QVDDL) of 1.25 V.
Object Code Compatible with the 56K core.
Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter;16 bit arithmatic support.
Program Control with position independent code support.
Six-channel DMA controller.
Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL feedback multiplier (2 or
4), Output divide factor (1, 2 or 4) and a power-saving clock divider (2
i
: i = 0 to 7) to reduce clock noise
Internal address tracing support and OnCE for Hardware/Software debugging.
JTAG port, supporting boundary scan, compliant to IEEE 1149.1.
Very low-power CMOS design, fully static design with operating frequencies down to DC.
STOP and WAIT low-power standby modes.
PRELIMINARY
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Features
1.2
•
•
•
•
•
On-chip Memory Configuration
6Kx24 Bit Y-Data RAM and 4Kx24 Bit Y-Data ROM.
6Kx24 Bit X-Data RAM and 4Kx24 Bit X-Data ROM.
20Kx24 Bit Program and Bootstrap ROM including a PROM patching mechanism.
6Kx24 Bit Program RAM.
Various memory switches are available. See memory table below.
Table 1. DSP56374 Memory Switch Configurations
Bit Settings
MSW1
X
0
0
1
1
MSW0
X
0
1
0
1
MS
0
1
1
1
1
Prog
RAM
6K
2K
4K
8K
10K
Memory Sizes (24-bit words)
X Data
RAM
6K
10K
8K
4K
4K
Y Data
RAM
6K
6K
6K
6K
4K
Prog
ROM
20K
20K
20K
20K
20K
X Data
ROM
4K
4K
4K
4K
4K
Y Data
ROM
4K
4K
4K
4K
4K
1.3
•
•
•
•
•
•
Peripheral modules
Enhanced Serial Audio Interface (ESAI): up to 4 receiver pins and up to 6 transmitter pins, master or slave. I
2
S, Sony,
AC97, network and other programmable protocols.
Enhanced Serial Audio Interface I (ESAI_1): up to 4 receiver pins and up to 6 transmitter pins, master or slave. I
2
S, Sony,
AC97, network and other programmable protocols.
Note: Available in the 80 pin package only
Serial Host Interface (SHI): SPI and I
2
C protocols, 10-word receive FIFO, support for 8, 16 and 24-bit words. Three noise
reduction filter modes.
Triple Timer module (TEC).
Most pins of unused peripherals may be programmed as GPIO pins. Up to 47 pins can be configured as GPIO on the
80 pin package and 20 pins on the 52 pin package.
Hardware Watchdog Timer
1.4
•
Packages
80-pin and 52-pin plastic LQFP packages.
Freescale Semiconductor
PRELIMINARY
3
Documentation
2
Documentation
Table 2
lists the documents that provide a complete description of the DSP56374 and are required to design properly with the
part. Documentation is available from a local Freescale Semiconductor, Inc. (formerly Motorola) distributor, semiconductor sales
office, Literature Distribution Center, or through the Freescale DSP home page on the Internet (the source for the latest
information).
Table 2. DSP56374 Documentation
Document Name
DSP56300 Family Manual
DSP56374 User’s Manual
DSP56374 Technical Data Sheet
DSP56374 Product Brief
Description
Detailed description of the 56300-family architecture and the
24-bit core processor and instruction set
Detailed description of memory, peripherals, and interfaces
Electrical and timing specifications; pin and package
descriptions
Brief description of the chip
Order Number
DSP56300FM/AD
DSP56374UM/D
DSP56374
DSP56374PB/D
3
Signal Groupings
The input and output signals of the DSP56374 are organized into functional groups, which are listed in Table 3..
The DSP56374 is operated from a 1.25 V and 3.3 V supply; however, some of the inputs can tolerate 5.0 V. A special notice for
this feature is added to the signal descriptions of those inputs.
Table 3. DSP56374 Functional Signal Groupings
Functional Group
Power (V
DD
)
Ground (GND)
Scan Pins
Clock and PLL
Interrupt and mode control
SHI
ESAI
ESAI_1
Dedicated GPIO
Timer
JTAG/OnCE Port
Note:
1.
2.
3.
4.
5.
Number of
Signals
1
11
9
1
3
Port H
2
Port H
2
Port C
4
Port E
5
Port G
3
5
5
12
12
15
3
4
Detailed
Description
Table 15.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Pins are not 5 V. tolerant unless noted.
Port H signals are the GPIO port signals which are multiplexed with the MOD and HREQ signals.
Port G signals are the dedicated GPIO port signals.
Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.
Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.
4
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Freescale Semiconductor
Signal Groupings
3.1
Power
Table 4. Power Inputs
Power Name
PLLA_VDD (1)
Description
PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 3.3 V
DD
power rail. The user must provide adequate
external decoupling capacitors between PLLA_VDD and PLLA_GND. PLLA_VDD requires a
filter as shown in Figure 21 and Figure 22 below. See the DSP56374 technical data sheet for
additional details.
PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 3.3 V
DD
power rail. The user must provide adequate
external decoupling capacitors between PLLP_VDD and PLLP_GND.
PLL Power— The voltage (1.25 V) should be well-regulated and the input should be provided
with an extremely low impedance path to the 1.25 V
DD
power rail. The user must provide
adequate external decoupling capacitors between PLLD_VDD and PLLD_GND.
Core Power—The voltage (1.25 V) should be well-regulated and the input should be provided
with an extremely low impedance path to the 1.25 V
DD
power rail. The user must provide
adequate external decoupling capacitors.
SHI, ESAI, ESAI_1, WDT and Timer I/O Power —The voltage (3.3 V) should be well-regulated,
and the input should be provided with an extremely low impedance path to the 3.3 V
DD
power
rail. This is an isolated power for the SHI, ESAI, ESAI_1, WDT and Timer I/O. The user must
provide adequate external decoupling capacitors.
PLLP_VDD(1)
PLLD_VDD (1)
CORE_VDD (4)
IO_VDD
(80-pin 4)
(52-pin 3)
3.2
Ground
Table 5. Grounds
Ground Name
PLLA_GND(1)
Description
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND.
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLP_VDD and PLLP_GND.
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors between PLLD_VDD and PLLD_GND.
Core Ground—The Core ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
SHI, ESAI, ESAI_1, WDT and Timer I/O Ground—IO_GND is the ground for the SHI, ESAI,
ESAI_1, WDT and Timer I/O. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
PLLP_GND(1)
PLLD_GND(1)
CORE_GND(4)
IO_GND(2)
Freescale Semiconductor
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