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SM59A16U1: 产品描述Instruction-set compatible with MCS-51; 文件大小2MB，共146页; 制造商SYNCMOS; 官网地址http://www.syncmos.com.tw/index.html

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SM59A16U1概述

Instruction-set compatible with MCS-51

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SM59A16U1

8-Bit Micro-controller

64KB with ISP Flash

& 6K+256B RAM embedded

Product List ................................................................................................................................................................. 6

Description .................................................................................................................................................................. 6

Ordering Information .................................................................................................................................................... 6

Features ...................................................................................................................................................................... 6

Pin Configuration ......................................................................................................................................................... 8

Block Diagram ............................................................................................................................................................. 9

Pin Description .......................................................................................................................................................... 10

Special Function Register ( SFR ) .............................................................................................................................. 13

Function Description .................................................................................................................................................. 22

General Features .......................................................................................................................................... 22

1.1

Embedded Flash ................................................................................................................................... 22

1.2

IO Pads ................................................................................................................................................ 22

1.3

2T/1T Selection..................................................................................................................................... 22

1.4

RESET ................................................................................................................................................. 23

1.4.1

Hardware RESET Function ........................................................................................................... 23

1.4.2

Software RESET Function ............................................................................................................ 23

1.4.3

Time Access Key Register( TAKEY ) ............................................................................................. 23

1.4.4

Software Reset Register( SWRES ) .............................................................................................. 23

1.4.5

Example Of Software Reset .......................................................................................................... 24

1.5

Clocks................................................................................................................................................... 24

Instruction Set ............................................................................................................................................... 25

Memory Structure .......................................................................................................................................... 29

3.1

Program Memory .................................................................................................................................. 29

3.2

Data Memory ........................................................................................................................................ 30

3.3

Data Memory - Lower 128 Byte( 00h to 7Fh ) ........................................................................................ 31

3.4

Data Memory - Higher 128 Byte( 80h to FFh ) ....................................................................................... 31

3.5

Data Memory - Expanded 6K Bytes( 0000h ~ 0x17FFh ) ....................................................................... 31

CPU Engine .................................................................................................................................................. 32

4.1

Accumulator.......................................................................................................................................... 33

4.2

B Register ............................................................................................................................................. 33

4.3

Program Status Word ( PSW ) ............................................................................................................... 34

4.4

Stack Pointer ( SP ) ............................................................................................................................... 34

4.5

Data Pointer( DP )................................................................................................................................. 34

4.6

Data Pointer 1( DP1 ) ............................................................................................................................ 35

4.7

Auxiliary Register( AUX ) ....................................................................................................................... 35

4.8

Internal RAM Control Register( RCON ) ................................................................................................ 36

4.9

Clock Control Register( CKCON ) ......................................................................................................... 36

4.10

Interface Control Register( IFCON ) ...................................................................................................... 37

4.11

Page Select( PAGESEL ) ...................................................................................................................... 37

4.12

PWM Address Register( PWMADDR )................................................................................................... 38

4.13

PWM Data Register( PWMDATA ) ......................................................................................................... 38

4.14

USB Address Register( USBADDR ) ..................................................................................................... 39

4.15

USB Data Register( USBDATA ) ............................................................................................................ 39

GPIO............................................................................................................................................................. 40

5.1

P0 ( Port 0 Register ) ............................................................................................................................ 40

5.2

P1 ( Port 1 Register) ............................................................................................................................. 40

5.3

P2 ( Port 2 Register ) ............................................................................................................................ 41

5.4

P3 ( Port 3 Register ) ............................................................................................................................ 41

5.5

P4 ( Port 4 Register ) ............................................................................................................................ 41

Multiplication Division Unit( MDU ) ................................................................................................................. 42

6.1

Operating Registers of the MDU............................................................................................................ 42

6.2

Operation of the MDU ........................................................................................................................... 43

6.2.1

First phase: loading the MDx registers, x = 0~5: ............................................................................ 43

6.2.2

Second phase: executing calculation. ........................................................................................... 43

6.2.3

Third phase: reading the result from the MDx registers.................................................................. 44

6.3

Normalizing........................................................................................................................................... 44

Specifications subject to change without notice contact your sales representatives for the most recent information.

ISSFD-M071

Ver A

SM59A16U1

04/12/2013

-1-

SM59A16U1

8-Bit Micro-controller

64KB with ISP Flash

& 6K+256B RAM embedded

Shifting ................................................................................................................................................. 45

Timer 0 and Timer 1 ...................................................................................................................................... 46

7.1

Timer/Counter Mode Vontrol Register (TMOD) ...................................................................................... 46

7.2

Timer/Counter Control Register( TCON ) ............................................................................................... 47

7.3

Timer 0 Register( TL0, TH0 ) ................................................................................................................. 48

7.4

Timer 1 Register( TL1, TH1 ) ................................................................................................................. 48

7.5

Peripheral Frequency Control Register .................................................................................................. 48

7.6

Mode 0( 13-bit Counter/Timer ) ............................................................................................................. 49

7.7

Mode 1( 16-bit Counter/Timer ) ............................................................................................................. 50

7.8

Mode 2( 8-bit auto-reload Counter/Timer ) ............................................................................................. 50

7.9

Mode 3( Timer 0 acts as two independent 8 bit Timers / Counters ) ....................................................... 51

Timer 2 and Capture Compare Unit ............................................................................................................... 52

8.1

Auxiliary 2 Register( AUX2 ) .................................................................................................................. 52

8.2

Timer 2 Control Register( T2CON ) ....................................................................................................... 53

8.3

Compare/Capture Control Register( CCCON ) ...................................................................................... 54

8.4

Compare/Capture Enable Register( CCEN ) .......................................................................................... 55

8.5

Compare/Capture Enable 2 Register( CCEN2 ) ..................................................................................... 55

8.6

Timer 2 Register( TL2, TH2 ) ................................................................................................................. 57

8.7

Compare/Reload/Capture Registers( CRCL, CRCH ) ............................................................................ 57

8.8

Compare/Capture Register 1( CCL1, CCH1 ) ........................................................................................ 57

8.9

Compare/Capture Register 2( CCL2, CCH2 ) ........................................................................................ 57

8.10

Compare/Capture Register 3( CCL3, CCH3 ) ........................................................................................ 57

8.11

Timer 2 Function ................................................................................................................................... 58

8.11.1

Timer Mode .............................................................................................................................. 58

8.11.2

Event Counter Mode................................................................................................................. 58

8.11.3

Gated Timer Mode .................................................................................................................... 59

8.11.4

Reload of Timer 2 ..................................................................................................................... 59

8.12

Compare Function ................................................................................................................................ 59

8.12.1

Compare Mode 0...................................................................................................................... 59

8.12.2

Compare Mode 1...................................................................................................................... 60

8.13

Capture Function .................................................................................................................................. 61

8.13.1

Capture Mode 0 ( by Hardware ) ............................................................................................... 61

8.13.2

Capture Mode 1( by Software ) ................................................................................................. 62

Serial Interface 0 and 1 ................................................................................................................................. 63

9.1

Serial Port 0 Control Register( S0CON )................................................................................................ 63

9.2

Serial Port 0 Reload Register( S0RELL, S0RELH ) ............................................................................... 64

9.3

Serial Port 0 Data Buffer( S0BUF ) ........................................................................................................ 64

9.4

Serial Port 1 Control Register( S1CON )................................................................................................ 64

9.5

Serial Port 1 Reload Register( S1RELL, S1RELH ) ............................................................................... 65

9.6

Serial Port 1 Data Buffer( S1BUF ) ........................................................................................................ 65

9.7

Serial Interface 0................................................................................................................................... 65

9.7.1

Mode 0 ......................................................................................................................................... 66

9.7.2

Mode 1 ......................................................................................................................................... 66

9.7.3

Mode 2 ......................................................................................................................................... 67

9.7.4

Mode 3 ......................................................................................................................................... 67

9.8

Serial Interface 1................................................................................................................................... 67

9.8.1

Mode A ......................................................................................................................................... 67

9.8.2

Mode B......................................................................................................................................... 68

9.9

Multiprocessor communication of Serial Interface 0 and 1 ..................................................................... 68

9.10

Baud Rate Generator ............................................................................................................................ 69

9.10.1

Serial Interface 0 modes 1 and 3 .............................................................................................. 69

9.10.2

Serial Interface 1 modes A and B .............................................................................................. 70

9.11

Clock Source for baud rate.................................................................................................................... 70

10.

Watchdog timer ............................................................................................................................................. 71

10.1

Watchdog Timer Control Register( WDTC ) ........................................................................................... 73

10.2

Watchdog Timer Refresh Register( WDTK ) .......................................................................................... 73

Specifications subject to change without notice contact your sales representatives for the most recent information.

ISSFD-M071

Ver A

SM59A16U1

04/12/2013

-2-

6.4

SM59A16U1

8-Bit Micro-controller

64KB with ISP Flash

& 6K+256B RAM embedded

11.

Interrupt ........................................................................................................................................................ 75

11.1

Interrupt Enable 0 Register( IEN0 )........................................................................................................ 76

11.2

Interrupt Enable 1 Register( IEN1 )........................................................................................................ 76

11.3

Interrupt Enable 2 Register( IEN2 )........................................................................................................ 77

11.4

Interrupt Request Register( IRCON ) ..................................................................................................... 77

11.5

Interrupt Request Register 2( IRCON2 ) ................................................................................................ 78

11.6

Priority Level Structure .......................................................................................................................... 78

Power Management Unit ............................................................................................................................... 80

12.1

Idle Mode .............................................................................................................................................. 80

12.2

Stop Mode ............................................................................................................................................ 80

Pulse Width Modulation ( PWM ) ................................................................................................................... 81

13.1

ADC Control Register 2( ADCC2 ) ......................................................................................................... 83

13.2

PWM Time Base Control 0( PWMTBC0 ) .............................................................................................. 84

13.3

PWM Time Base Control 1( PWMTBC1 ) .............................................................................................. 85

13.4

PWM Output Pair Mode( PWMOPMOD ) .............................................................................................. 85

13.5

Time Base Counter by PWM clock( TBCOUNTERL, TBCOUNTERH )................................................... 86

13.6

PWM Period( PERIODL, PERIODH ) .................................................................................................... 86

13.7

Special Event Compare( SEVTCMPL, SEVTCMPH )............................................................................. 86

13.8

PWM Output Enable( PWMEN ) ............................................................................................................ 86

13.9

PWM Special Event( PWMSEV ) ........................................................................................................... 87

13.10

PWM Time Base Post Scale Register( PWMTBPOSTSCALE) .......................................................... 88

13.11

PWM Interrupt Flag(PWMINTF ) ....................................................................................................... 88

13.12

Dead Time ........................................................................................................................................ 89

13.12.1

Dead Time 0 for PWM Pair 0( DEADTIME0 ) ............................................................................ 90

13.12.2

Dead Time 1 for PWM Pair 1( DEADTIME1 ) ............................................................................ 90

13.12.3

Dead Time 2 for PWM Pair 2( DEADTIME2 ) ............................................................................ 90

13.12.4

Dead Time 3 for PWM Pair 3( DEADTIME3 ) ............................................................................ 91

13.12.5

Override Disable( OVRIDEDIS ) ............................................................................................... 91

13.12.6

Override Data ( OVRIDEDATA ) ................................................................................................ 92

13.12.7

PWM Polarity ( PWMPOLARITY )............................................................................................. 93

13.13

Fault Configure ( FLTCONFIG ) ........................................................................................................ 94

13.14

PWM Fault Inputs ............................................................................................................................. 94

13.15

Fault Noise Filter( FLTNF ) ................................................................................................................ 95

13.16

PWM Pair 0 Duty( DUTY0L, DUTY0H ) ............................................................................................. 95

13.17

PWM Pair 1 Duty( DUTY1L, DUTY1H ) ............................................................................................. 95

13.18

PWM Pair 2 Duty( DUTY2L, DUTY2H ) ............................................................................................. 96

13.19

PWM Pair 3 Duty( DUTY3L, DUTY3H ) ............................................................................................. 96

IIC function .................................................................................................................................................... 97

14.1

IIC Control Register( IICCTL ) ............................................................................................................... 97

14.2

IIC Status Register( IICS ) ..................................................................................................................... 98

14.3

IIC Address1 Register( IICA1 ) .............................................................................................................. 99

14.4

IIC Address2 Register( IICA2 ) ............................................................................................................ 101

14.5

IIC Read Write Register( IICRWD ) ..................................................................................................... 101

14.6

IIC Enable Bus Transaction Register( IICEBT ).................................................................................... 101

SPI Function - Serial Peripheral Interface .................................................................................................... 103

15.1

SPI Control Register 1( SPIC1 ) .......................................................................................................... 104

15.2

SPI Control Register 2( SPIC2 ) ......................................................................................................... 105

15.3

SPI Status Register (SPIS ) ................................................................................................................. 106

15.4

SPI Transmit Data Buffer (SPITXD ) .................................................................................................... 107

15.5

SPI Receive Data Buffer (SPIRXD) ..................................................................................................... 107

KBI – Keyboard Interface............................................................................................................................. 108

16.1

Keyboard Level Selector Register( KBLS ) .......................................................................................... 109

16.2

Keyboard Interrupt Enable Register( KBE ) .......................................................................................... 110

16.3

Keyboard Interrupt Flag Register( KBF )............................................................................................... 110

16.4

Keyboard De-bounce Control Register( KBD ) ...................................................................................... 112

LVI & LVR – Low Voltage Interrupt and Low Voltage Reset ........................................................................... 113

12.

13.

14.

15.

16.

17.

Specifications subject to change without notice contact your sales representatives for the most recent information.

ISSFD-M071

Ver A

SM59A16U1

04/12/2013

-3-

SM59A16U1

8-Bit Micro-controller

64KB with ISP Flash

& 6K+256B RAM embedded

17.1

Low Voltage Control Register( LVC ) .................................................................................................... 113

10-bit Analog-to-Digital Converter ( ADC ) ..................................................................................................... 114

18.1

ADC Control Register 1( ADCC1 ) ........................................................................................................ 114

18.2

ADC Control Register 2( ADCC2 ) ........................................................................................................ 115

18.3

ADC Data( ADCDH, ADCDL )............................................................................................................... 115

18.4

ADC Clock Select( ADCCS ) ................................................................................................................ 116

USB function ................................................................................................................................................ 117

19.1

USB Device Enumeration Transfer ....................................................................................................... 117

19.2

USB Interrupt In Transfer ..................................................................................................................... 117

19.3

USB Interrupt Out Transfer ................................................................................................................... 117

19.4

USB Bulk Transfer From Host to Device ............................................................................................... 118

19.5

USB Bulk Transfer From Device to Host ............................................................................................... 118

19.6

USB Control 1 Register( UCTRL1 ) ..................................................................................................... 120

19.7

USB Control 2 Register( UCTRL2 ) .................................................................................................... 121

19.8

USB Status Register( USTAT ) ............................................................................................................ 121

19.9

USB Device Address Register( DEVADR ) .......................................................................................... 122

19.10

USB Frame Number Register( FRMNUMH, FRMNUML ) ................................................................ 122

19.11

USB Host Stall Register( HSTALL ) ................................................................................................. 122

19.12

USB Device Stall Register( DSTALL ) .............................................................................................. 123

19.13

USB Handshake Status Register( HSKSTAT ) ................................................................................. 123

19.14

USB Interrupt Enable Register 1( UIER1 ) ....................................................................................... 125

19.15

USB Interrupt Enable Register 2( UIER2 ) ....................................................................................... 125

19.16

USB Interrupt Flag Register 1( UIFR1 ) ........................................................................................... 126

19.17

USB Interrupt Flag Register 2( UIFR2 ) ........................................................................................... 126

19.18

USB Endpoint Data Ready Register( EPDRDY ) ............................................................................. 127

19.19

USB Endpoint 0 Data Counter Register( EP0CNT ) ......................................................................... 128

19.20

USB Endpoint 1 Data Counter Register( EP1CNT ) ......................................................................... 128

19.21

USB Endpoint 2 Data Counter Register( EP2CNT ) ......................................................................... 128

19.22

USB Endpoint 3 Data Counter Register( EP3CNT ) ......................................................................... 128

19.23

USB Endpoint 4 Data Counter Register( EP4CNT ) ......................................................................... 129

19.24

USB Endpoint 0 Data Register( EP0DATA ) .................................................................................... 129

19.25

USB Endpoint 1 Data Register( EP1DATA )..................................................................................... 129

19.26

USB Endpoint 2 Data Register( EP2DATA )..................................................................................... 129

19.27

USB Endpoint 3 Data Register( EP3DATA )..................................................................................... 130

19.28

USB Endpoint 4 Data Register( EP4DATA )..................................................................................... 130

Barcode ...................................................................................................................................................... 131

20.1

Barcode Control Register( BCCTRL ) .................................................................................................. 131

20.2

Start Address to SRAM Register( ADDR2ML, ADDR2MH ) .................................................................. 132

20.3

Length of Data Register( LNGDATAL, LNGDATAH ) ............................................................................ 133

20.4

Rising of Data Register( RDATA ) ........................................................................................................ 133

20.5

Falling of Data Register( FDATA ) ........................................................................................................ 133

In-System Programming ( Internal ISP )....................................................................................................... 134

21.1

ISP service program............................................................................................................................ 134

21.2

Lock Bit ( N ) ....................................................................................................................................... 134

21.3

Program the ISP Service Program....................................................................................................... 135

21.4

Initiate ISP Service Program ............................................................................................................... 135

21.5

ISP register – TAKEY, IFCON, ISPFAH, ISPFAL, ISPFD and ISPFC.................................................... 136

21.6

Time Access Key Register( TAKEY ) ................................................................................................... 136

21.7

Interface Control Register( IFCON ) .................................................................................................... 137

21.8

ISP Flash Address Register( ISPFAH, ISPFAL ) .................................................................................. 137

21.9

ISP Flash Data Register( ISPFD ) ....................................................................................................... 137

21.10

ISP Flash Control Register( ISPFC ) ............................................................................................... 137

OPA/Comparator ......................................................................................................................................... 139

22.1

Op/Comparator Pin Select( OpPin )..................................................................................................... 140

22.2

Op/Comparator Pin Select 2( OpPin2 ) ................................................................................................ 141

22.3

Comparator 0 Control( Cmp0CON ) .................................................................................................... 141

18.

19.

20.

21.

22.

Specifications subject to change without notice contact your sales representatives for the most recent information.

ISSFD-M071

Ver A

SM59A16U1

04/12/2013

-4-

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