SN54HC365, SN74HC365
HEX BUFFERS AND LINE DRIVERS
WITH 3 STATE OUTPUTS
SCLS308D − JANUARY 1996 − REVISED OCTOBER 2003
D
Wide Operating Voltage Range of 2 V to 6 V
D
High-Current 3-State Outputs Drive Bus
D
D
D
D
D
Lines, Buffer-Memory Address Registers,
or Drive Up To 15 LSTTL Loads
True Outputs
Low Power Consumption, 80-µA Max I
CC
Typical t
pd
= 10 ns
±6-mA
Output Drive at 5 V
Low Input Current of 1
µA
Max
SN54HC365 . . . J OR W PACKAGE
SN74HC365 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
description/ordering information
These hex buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. The ’HC365 devices contain six
independent buffers/drivers with dual-gated
output-enable (OE1 and OE2) inputs. When OE1
and OE2 are both low, the devices pass
noninverted data from the A inputs to the
Y outputs. If either (or both) output-enable
terminal(s) is high, the outputs are in the
high-impedance state.
OE1
A1
Y1
A2
Y2
A3
Y3
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
OE2
A6
Y6
A5
Y5
A4
Y4
SN54HC365 . . . FK PACKAGE
(TOP VIEW)
A1
OE1
NC
V
CC
OE2
Y1
A2
NC
Y2
A3
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
A6
Y6
NC
A5
Y5
NC − No internal connection
ORDERING INFORMATION
TA
PDIP − N
PACKAGE†
Tube of 25
Tube of 40
SOIC − D
−40°C to 85°C
SOP − NS
Reel of 2500
Reel of 250
Reel of 2000
Reel of 90
TSSOP − PW
CDIP − J
−55 C 125°C
−55°C to 125 C
CFP − W
LCCC − FK
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
ORDERABLE
PART NUMBER
SN74HC365N
SN74HC365D
SN74HC365DR
SN74HC365DT
SN74HC365NSR
SN74HC365PW
SN74HC365PWR
SN74HC365PWT
SNJ54HC365J
SNJ54HC365W
SNJ54HC365FK
SNJ54HC365J
SNJ54HC365W
SNJ54HC365FK
HC365
HC365
HC365
TOP-SIDE
MARKING
SN74HC365N
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
Y3
GND
NC
Y4
A4
1
SCLS308D − JANUARY 1996 − REVISED OCTOBER 2003
SN54HC365, SN74HC365
HEX BUFFERS AND LINE DRIVERS
WITH 3 STATE OUTPUTS
FUNCTION TABLE
(each buffer/driver)
INPUTS
OE1
H
X
L
L
OE2
X
H
L
L
A
X
X
H
L
OUTPUT
Y
Z
Z
H
L
logic diagram (positive logic)
OE1
OE2
1
15
A1
2
3
Y1
To Five Other Channels
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±35
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±70
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54HC365, SN74HC365
HEX BUFFERS AND LINE DRIVERS
WITH 3 STATE OUTPUTS
SCLS308D − JANUARY 1996 − REVISED OCTOBER 2003
recommended operating conditions (see Note 3)
SN54HC365
MIN
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VIL
VI
VO
∆t/∆v
Low-level input voltage
Input voltage
Output voltage
VCC = 2 V
VCC = 4.5 V
VCC = 6 V
VCC = 4.5 V
VCC = 6 V
0
0
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
0
0
NOM
5
MAX
6
SN74HC365
MIN
2
1.5
3.15
4.2
0.5
1.35
1.8
VCC
VCC
1000
500
400
ns
V
V
V
V
NOM
5
MAX
6
UNIT
V
High-level input voltage
Input transition rise/fall time
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2V
IOH = −20
µA
VOH
VI = VIH or VIL
IOH = −6 mA
IOH = −7.8 mA
IOL = 20
µA
VOL
VI = VIH or VIL
IOL = 6 mA
IOL = 7.8 mA
II
IOZ
ICC
Ci
VI = VCC or 0
VO = VCC or 0
VI = VCC or 0,
IO = 0
4.5 V
6V
4.5 V
6V
2V
4.5 V
6V
4.5 V
6V
6V
6V
6V
2 V to 6 V
3
TA = 25°C
MIN
TYP
MAX
1.9
4.4
5.9
3.98
5.48
1.998
4.499
5.999
4.3
5.8
0.002
0.001
0.001
0.17
0.15
±0.1
±0.01
0.1
0.1
0.1
0.26
0.26
±100
±0.5
8
10
SN54HC365
MIN
1.9
4.4
5.9
3.7
5.2
0.1
0.1
0.1
0.4
0.4
±1000
±10
160
10
MAX
SN74HC365
MIN
1.9
4.4
5.9
3.84
5.34
0.1
0.1
0.1
0.33
0.33
±1000
±5
80
10
nA
µA
µA
pF
V
V
MAX
UNIT
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SCLS308D − JANUARY 1996 − REVISED OCTOBER 2003
SN54HC365, SN74HC365
HEX BUFFERS AND LINE DRIVERS
WITH 3 STATE OUTPUTS
switching characteristics over recommended operating free-air temperature range, C
L
= 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
tpd
A
Y
4.5 V
6V
2V
ten
OE
Y
4.5 V
6V
2V
tdis
OE
Y
4.5 V
6V
2V
tt
Any
4.5 V
6V
TA = 25°C
MIN
TYP
MAX
50
12
10
100
26
21
50
21
19
28
8
6
95
19
16
190
38
32
175
35
30
60
12
10
SN54HC365
MIN
MAX
145
29
25
285
57
48
265
53
45
90
18
15
SN74HC365
MIN
MAX
120
24
20
238
48
41
240
48
41
75
15
13
ns
ns
ns
ns
UNIT
switching characteristics over recommended operating free-air temperature range, C
L
= 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
2V
tpd
A
Y
4.5 V
6V
2V
ten
OE
Y
4.5 V
6V
2V
tt
Any
4.5 V
6V
TA = 25°C
MIN
TYP
MAX
70
17
14
140
30
28
45
17
13
120
24
20
230
46
39
210
42
36
SN54HC365
MIN
MAX
180
36
31
345
69
59
315
63
53
SN74HC365
MIN
MAX
150
30
25
285
57
48
265
53
45
ns
ns
ns
UNIT
operating characteristics, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance per buffer/driver
TEST CONDITIONS
No load
TYP
35
UNIT
pF
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54HC365, SN74HC365
HEX BUFFERS AND LINE DRIVERS
WITH 3 STATE OUTPUTS
SCLS308D − JANUARY 1996 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
VCC
PARAMETER
Test
Point
S1
RL
ten
tPZH
tPZL
tPHZ
tPLZ
1 kΩ
RL
CL
50 pF
or
150 pF
50 pF
50 pF
or
150 pF
S1
Open
Closed
Open
Closed
−−
Open
S2
Closed
Open
Closed
Open
Open
From Output
Under Test
CL
(see Note A)
S2
tdis
1 kΩ
tpd or tt
LOAD CIRCUIT
VCC
Input
50%
tPLH
In-Phase
Output
50%
10%
tPHL
Out-of-Phase
Output
90%
50%
10%
tf
90%
tr
tPLH
50%
10%
90%
tr
VOH
VOL
50%
0V
tPHL
90%
VOH
50%
10% V
OL
tf
Output
Control
(Low-Level
Enabling)
tPZL
Output
Waveform 1
(See Note B)
tPZH
VCC
50%
50%
0V
tPLZ
≈V
CC
50%
10%
tPHZ
50%
90%
VOH
≈0
V
≈V
CC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
VCC
50%
10% 0 V
tf
Input
50%
10%
90%
90%
Output
Waveform 2
(See Note B)
tr
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 6 ns, tf = 6 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
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