Freescale Semiconductor
Errata
DSP56311CE1K34A
Rev. 5, 11/2004
DSP56311 Device Errata for Mask
1K34A
General remark: In order to prevent the use of instructions or sequences of instructions that do not operate correctly,
we encourage you to use the “lint563” program to identify such cases and use alternative sequences of instructions.
This program is available as part of the Freescale DSP Tools CLAS package.
Silicon Errata
Errata
Number
Errata Description
None known.
Applies
to Mask
1K34A
© Freescale Semiconductor, Inc., 1997–2004. All rights reserved.
Documentation Errata
Documentation Errata
Description (revised 11/9/98):
XY memory data move does not work properly under one of the following two
situations:
1.
The X-memory move destination is internal I/O and the Y-memory
1K34A
move source is a register used as destination in the previous adjacent
move from non Y-memory
2.
The Y-memory move destination is a register used as source in the next
adjacent move to non Y-memory.
Here are examples of the two cases (where x:(r1) is a peripheral):
Example 1:
move #$12,y0
move x0,x:(r7) y0,y:(r3) (while x:(r7) is a peripheral).
ED1
Example 2:
mac
move
x1,y0,a x1,x:(r1)+
y0,y1
y:(r6)+,y0
Any of the following alternatives can be used:
1.
Separate these two consecutive moves by any other instruction.
2.
Split XY Data Move to two moves.
Pertains to:
DSP56300 Family Manual, Section B-5 “Peripheral pipeline
restrictions.
Description (added before 2/18/1996):
1K34A
ED3
BL pin timings T198 and T199 in the data sheet are changed, improving the
arbitration latency: T198 is 5 ns (max), T199 is 0 ns (min).
Pertains to:
Data Sheet, Synchronous Timings (SRAM) table, Table 2-17.
Description (added 1/27/98):
When activity is passed from one DMA channel to another and the DMA interface
accesses external memory (which requires one or more wait states), the DACT and
DCH status bits in the DMA Status Register (DSTR) may indicate improper activity
status for DMA Channel 0 (DACT = 1 and DCH[2:0] = 000).
Workaround: None.
This is not a bug, but a specification update.
1K34A
ED7
DSP56311 Device Errata for Mask 1K34A, Rev. 5
2
Freescale Semiconductor
Documentation Errata
Description (added 1/27/98):
When the SCI is configured in Synchronous mode, internal clock, and all the SCI
pins are enabled simultaneously, an extra pulse of 1 DSP clock length is provided on
the SCLK pin.
1K34A
ED9
Workaround:
1.
Enable an SCI pin other than SCLK.
2.
In the next instruction, enable the remaining SCI pins, including the
SCLK pin.
This is not a bug, but a specification update.
Description (added 7/21/98):
The DRAM Control Register (DCR) should not be changed while refresh is
enabled. If refresh is enabled only a write operation that disables refresh is allowed.
Workaround:
First disable refresh by clearing the BREN bit, than change other bits in the DCR
register, and finally enable refresh by setting the BREN bit.
Description (added 9/28/98):
In all DSP563xx technical data sheets, a note is to be added under “AC Electrical
Characteristics” that although the minimum value for “Frequency of Extal” is
0MHz, the device AC test conditions are 15MHz and rated speed.
Workaround:
N/A
Description (added 11/24/98):
1K34A
ED15
1K34A
ED17
1K34A
ED20
In the Technical Data sheet Voh-TTL should be listed at 2.4 Volts, not as:
TTL = Vcc-0.4
Workaround: This is a documentation update.
Description (added 11/24/98):
1K34A
ED24
The technical data sheet supplies a maximum value for internal supply current in
Normal, Wait, and Stop modes. These values will be removed because we will
specify only a “Typical” current.
Workaround: This is a documentation update.
Description (added 1/6/99):
The specification DMA Chapter is wrong.
1K34A
ED26
“Due to the DSP56300 Core pipeline, after DE bit in DCRx is set, the corresponding
DTDx bit in DSTR will be cleared only after two instruction cycles.”
Should be replaced with:
“Due to the DSP56300 Core pipeline, after DE bit in DCRx is set, the corresponding
DTDx bit in DSTR will be cleared only after three instruction cycles.”
DSP56311 Device Errata for Mask 1K34A, Rev. 5
Freescale Semiconductor
3
Documentation Errata
Description (added 1/7/1997; identified as Documentation Errata 2/1/99):
When two consecutive LAs have a conditional branch instruction at LA-1 of the
internal loop, the part does not operate properly. For example, the following
sequence may generate incorrect results:
DO #5, LABEL1
NOP
DO #4, LABEL2
NOP
MOVE (R0) +
BSCC _DEST
internal loop
NOP
LABEL2
NOP
LABEL1
NOP
NOP
_DEST NOP
NOP
RTS
1K34A
; conditional branch at LA-1 of
; internal LA
; external LA
ED28
Workaround: Put an additional NOP between LABEL2 and LABEL1.
Pertains to:
DSP56300 Family Manual, Appendix B, Section B-4.1.3, “At LA-1.”
Description (added 9/12/1997; identified as a Documentation errata 2/1/99):
When the ESSI transmits data with the CRA Word Length Control bits
(WL[2:0]) = 100, the ESSI is designed to duplicate the last bit of the 24-bit
transmission eight times to fill the 32-bit shifter. Instead, after shifting the 24-bit
word correctly, eight 0s are being shifted.
Workaround:
None at this time.
Pertains to:
UM, Section 7.4.1.7, “CRA Word Length Control.” The table number
is 7-2.
Description (added 9/12/1997; identified as a Documentation errata 2/1/99):
When the ESSI transmits data in the On-Demand mode (i.e., MOD = 1 in CRB and
DC[4:0] = $00000 in CRA) with WL[2:0] = 100, the transmission does not work
properly.
1K34A
ED29
1K34A
ED30
Workaround:
To ensure correct operation, do not use the On-Demand mode with the
WL[2:0] = 100 32-bit Word-Length mode.
Pertains to:
UM, Section 7.5.4.1, “Normal/On-Demand Mode Selection.”
DSP56311 Device Errata for Mask 1K34A, Rev. 5
4
Freescale Semiconductor
Documentation Errata
Description (added 9/12/1997; modified 9/15/1997; identified as a Documentation
errata 2/1/99):
Programming the ESSI to use an internal frame sync (i.e., SCD2 = 1 in CRB) causes
the SC2 and SC1 signals to be programmed as outputs. If however, the
corresponding multiplexed pins are programmed by the Port Control Register
(PCR) to be GPIOs, then the GPIO Port Direction Register (PRR) chooses their
direction, but this causes the ESSI to use an external frame sync if GPIO is selected.
Note:
This errata and workaround apply to both ESSI0 and
ESSI1.
Workaround: To assure correct operation, either program the GPIO pins as outputs
or configure the pins in the PCR as ESSI signals.
Note:
The default selection for these signals after reset is GPIO.
Pertains to:
UM, Section 7.4.2.4, “CRB Serial Control Direction 2 (SCD2) Bit 4”
Description (added 11/9/98; identified as a Documentation errata 2/1/99):
When returning from a long interrupt (by RTI instruction), and the first instruction
after the RTI is a move to a DALU register (A, B, X, Y), the move may not be
correct, if the 16-bit arithmetic mode bit (bit 17 of SR) is changed due to the
restoring of SR after RTI.
1K34A
ED31
1K34A
ED32
Workaround: Replace the RTI with the following sequence:
movec
nop
rti
ssl,sr
Pertains to:
DSP56300 Family Manual. Add a new section to Appendix B that is
entitled “Sixteen-Bit Compatibility Mode Restrictions.”
DSP56311 Device Errata for Mask 1K34A, Rev. 5
Freescale Semiconductor
5
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