MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
Freescale Semiconductor, Inc.
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Advance Information
DSP56156
DSP56156ROM
16-bit Digital Signal Processor
The DSP56156 is a general-purpose MPU-style Digital Signal Processor (DSP). On a single semi-
conductor chip, the DSP56156 comprises a very efficient 16-bit digital signal processing core, pro-
gram and data memories, a number of peripherals, and system support circuitry. Unique features
of the DSP56156 include a built-in sigma-delta (²½) codec and phase-locked loop (PLL). This com-
bination of features makes the DSP56156 a cost-effective, high-performance solution for many DSP
applications, especially speech coding, digital communications, and cellular base stations.
The central processing unit of the DSP56156 is the DSP56100 core processor. Like all DSP56100-
based DSPs, the DSP56156 consists of three execution units operating in parallel, allowing up to
six operations to be performed during each instruction cycle. This parallelism greatly increases the
effective processing speed of the DSP56156. The MPU-style programming model and instruction
set allow straightforward generation of efficient, compact code. The basic architectures and devel-
opment tools of Motorola's 16-bit, 24-bit, and 32-bit DSPs are so similar that understanding how to
design and program one greatly reduces the time needed to learn the others.
On-Chip Emulation (OnCE
TM
port) circuitry provides convenient and inexpensive debug facil-
ities normally available only through expensive external hardware. Development costs are re-
duced and in-field testing is greatly simplified using the OnCE
TM
port. Figure 1 illustrates the
DSP56156 in detail.
16-bit Bus
7
Sigma-
Delta
Codec
2
16-bit
Timer/
Event
Counter
5
Sync.
Serial
(SSI)
or
I/O
5
Sync.
Serial
(SSI)
or
I/O
15
Host
Interface
(HI)
or
I/O
Program
Memory *
2048
×
16 RAM
64
×
16 ROM
(boot)
Freescale Semiconductor, Inc...
Data
Memory
2048
×
16 RAM
16-bit
56100 DSP
Core
Internal
Data
Bus
Switch
OnCE™ Port
PLL
3
Clock
Gen.
Interrupt
Control
Address
Generation
Unit
PAB
XAB1
XAB2
GDB
PDB
XDB
External
Address
Bus
Switch
External
Data
Bus
Switch
Address
16
Data
16
Program
Decode
Controller
Program
Address
Generator
Program Control Unit
4 IRQ
2
Data ALU
16 x 16 + 40 —> 40-bit MAC
Two 40-bit Accumulators
Bus
Control
Control
9
* 12 k x 16 ROM replaces the program RAM on the DSP56156ROM
Figure 1
DSP56156 Block Diagram
Specifications and information herein are subject to change without notice.
OnCE is a trademark of Motorola, Inc.
©
MOTOROLA INC., 1994
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Freescale Semiconductor, Inc.
Introduction
DSP56156 Features
DSP56156 Features
Digital Signal Processing Core
• Efficient, object code compatible, 16-bit 56100-Family DSP engine
—
—
—
—
—
—
—
—
—
—
—
—
—
Up to 30 Million Instructions Per Second (MIPS) – 33 ns instruction cycle at 60 MHz
Up to 180 Million Operations Per Second (MOPS) at 60 MHz
Highly parallel instruction set with unique DSP addressing modes
Two 40-bit accumulators including extension byte
Parallel 16
×
16-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
Double precision 32
×
32-bit multiply with 72-bit result in 6 instruction cycles
Least Mean Square (LMS) adaptive loop filter in 2 instructions
40-bit Addition/Subtraction in 1 instruction cycle
Fractional and integer arithmetic with support for multiprecision arithmetic
Hardware support for block-floating point FFT
Hardware-nested DO loops including infinite loops
Zero-overhead fast interrupts (2 instruction cycles)
Three 16-bit internal data buses and three 16-bit internal address buses for
maximum information transfer on-chip
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Memory
• On-chip Harvard architecture permitting simultaneous accesses to program
and memories
• 2048
×
16-bit on-chip program RAM and 64
×
16-bit bootstrap ROM
(or 12 k
×
16-bit on-chip program ROM on the DSP56156ROM)
• 2048
×
16-bit on-chip data RAM
• External memory expansion with 16-bit address and data buses
• Bootstrap loading from external data bus, Host Interface, or
Synchronous Serial Interface
Peripheral and Support Circuits
• Byte-wide Host Interface (HI) with Direct Memory Access support
• Two Synchronous Serial Interfaces (SSI) to communicate with codecs and
synchronous serial devices
— Built in µ-law and A-law compression/expansion
— Up to 32 software-selectable time slots in network mode
• 16-bit Timer/Event Counter also generates and measures digital waveforms
• On-chip sigma-delta voice band Codec:
—
—
—
—
2
Sampling clock rates between 100 kHz and 3 MHz
Four software-programmable decimation/interpolation ratios
Internal voltage reference (
2
/
5
of positive power supply)
No external components required
DSP56156 Data Sheet
For More Information On This Product,
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MOTOROLA
Freescale Semiconductor, Inc.
Introduction
DSP56156 Features
Documentation
• On-chip peripheral registers memory mapped in data memory space
• Double buffered peripherals
• Up to 27 general purpose I/O pins
• Two external interrupt request pins
• On-Chip Emulation (OnCE™) port for unobtrusive, processor speed-independent
debugging
• Software-programmable, Phase-Locked Loop-based (PLL) frequency synthesizer for the
core clock
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Miscellaneous Features
• Power-saving Wait and Stop modes
• Fully static, HCMOS design for operating frequencies from 40 or 60 MHz down to DC
• 112-pin Ceramic Quad Flat Pack (CQFP) surface-mount package; 20
×
20
×
3 mm
• 112-pin Plastic Thin Quad Flat Pack (TQFP) surface-mount package; 20
×
20
×
1.5 mm
• 5 V power supply
Product Documentation
This data sheet plus the two manuals listed in Table 1 are required for a complete DSP56156
description and are necessary to properly design with the part. Documentation is available
from a local Motorola distributor, a semiconductor sales office, or through a Motorola Litera-
ture Distribution Center.
Table 1
DSP56156 Documentation
Topic
DSP56100 Family Manual
Description
Detailed description of the 56000-
family architecture and the 16-bit core
processor and instruction set
Detailed description of memory,
peripherals, and interfaces
Pin and package descriptions, and
electrical and timing specifications
Order Number
DSP56100FAMUM/AD
DSP56156 User’s Manual
DSP56156 Data Sheet
DSP56156UM/AD
DSP56156/D
MOTOROLA
DSP56156 Data Sheet
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Freescale Semiconductor, Inc.
Introduction
Documentation
Data Sheet Contents
Related Documentation
Table 2 lists additional documentation relevant to the DSP56156.
Table 2
Related Motorola Documentation
Topic
DSP Family Brochure
Description
Overview of all DSP product families
Product Brief. Includes ordering
information
Application Report. Includes code
Application Report. Comprehensive
FFT algorithms and code for
DSP56001, DSP56156, and
DSP96002
Application Report. Theory and code
using SB-ADPCM
Flyer. Motorola’s electronic bulletin
board where free DSP software is
available
Brochures from companies selling
hardware and software that supports
Motorola DSPs
Flyer. Motorola’s program that sup-
ports universities in DSP research
and education
Order Number
BR1105/D
DSPTOOLSP/D
APR3/D
APR4/D
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Development Tools
Fractional and Integer Arithmetic
Fast Fourier Transforms (FFTs)
G.722 Audio Processing
Dr. BuB Bulletin Board
APR404/D
BR297/D
Third Party Compendium
DSP3RDPTYPAK/D
University Support Program
BR382/D
Data Sheet Contents
This data sheet contains:
•
•
•
•
•
signal definitions and pin locations
electrical specifications and timings
package descriptions
design considerations
ordering information
4
DSP56156 Data Sheet
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Freescale Semiconductor, Inc.
Introduction
Pin Groupings
Pin Groupings
The DSP56156 is available in a 112-pin Ceramic Quad Flat Pack (CQFP) and a 112-pin Plastic
Thin Quad Flat Pack (TQFP). The input and output signals are organized into the functional
groups indicated in Table 3. Figure 2 illustrates the chip’s pin functions.
Table 3
Functional Pin Groupings
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Functional Group
Address
Data Bus
Bus Control
Host Interface (HI)
Synchronous Serial Interfaces (SSI)
Timer Interface
Interrupt and Mode Control
Phase-Locked Loop (PLL) and Clock
On-Chip Emulation (OnCE
TM
Port)
On-Chip Codec
Power (V
CC
)
Ground (GND)
Total
Number of Pins
16
16
9
15
10
2
4
3
4
7
10
16
112
NOTE:
OVERBARS are used throughout this document to indicate a signal which is at Ground voltage (typi-
cally a TTL logic low — V
IL
or V
OL
) when the function is logically true. These signals are, likewise, at
V
CC
voltage (typically a TTL logic high — V
IH
or V
OH
) when the function is logically false.
MOTOROLA
DSP56156 Data Sheet
For More Information On This Product,
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