KM4132G512A
CMOS SGRAM
16Mbit SGRAM
256K x 32bit x 2 Banks
Synchronous Graphic RAM
LVTTL
Revision 1.2
July 1999
Samsung Electronics reserves the right to change products or specification without notice.
-1-
Rev. 1.2 (Jul. 1999)
KM4132G512A
Revision History
Revision 1.2 (July 14th, 1999)
• Remove -10 part.
CMOS SGRAM
Revision 1.1 (June 23th, 1999)
• Add -10 part.
Revision 1.0 (June 10th, 1999) -
Final Spec
• AC values of tRCD/tRP/tRAS/tRC are returned to the number of clock cycles. Those can be also converted to ns unit
based values by multiplying the number of clock cycles and clock cycle time of each part together. Accordingly,
- Changed tRCD and tRP of KM4132G512A-5/7/8 each from 18ns to 20ns/21ns/20ns
- Changed tRC of KM4132G512A-7/8 each from 67ns/68ns to 70ns
- Changed tRC of KM4132G512A-5 from 65ns(13CLK) to 60ns (12CLK)
- Changed tRC of KM4132G512A-6 from 66ns(11CLK) to 60ns (10CLK)
• Add KM4132G512A-C(183MHz@CL3) part .For -C part, tRDL=1CLK can be supported within restricted amounts and it
will be distingusihed by bucket code "NV"
Revision 0.1 (April 1999)
- Preliminary Spec
• Changed I
LI
and
I
LO
from +/- 5uA to +/-10uA.
• Changed tSAC and tSHZ of KM4132G512A-8@CL2 from 7ns to 6ns.
Revision 0.0 (March 1999)
• First edition
-2-
Rev. 1.2 (Jul. 1999)
CMOS SGRAM
256K x 32Bit x 2 Banks Synchronous Graphic RAM
FEATURES
•
•
•
•
3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-. CAS Latency (2, 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the
system clock
Burst Read Single-bit Write operation
DQM 0-3 for byte masking
Auto & self refresh
32ms refresh period (2K cycle)
100 Pin PQFP, TQFP (14 x 20 mm)
GENERAL DESCRIPTION
The KM4132G512A is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 262,144 words by 32 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length, and programmable latencies allows the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
Write per bit and 8 columns block write improves performance in
graphics systems.
•
•
•
•
•
•
ORDERING INFORMATION
Part NO.
KM4132G512AQ-5/F5
KM4132G512AQ-C/FC
KM4132G512AQ-6/F6
KM4132G512AQ-7/F7
KM4132G512AQ-8/F8
KM4132G512ATQ-5/F5
KM4132G512ATQ-C/FC
KM4132G512ATQ-6/F6
KM4132G512ATQ-7/F7
KM4132G512ATQ-8/F8
Max Freq.
200MHz
183MHz
166MHz
143MHz
125MHz
200MHz
183MHz
166MHz
143MHz
125MHz
Interface
Package
Graphics Features
• SMRS cycle.
-. Load mask register
-. Load color register
• Write Per Bit(Old Mask)
• Block Write(8 Columns)
LVTTL
100 PQFP
LVTTL
100 TQFP
FUNCTIONAL BLOCK DIAGRAM
DQMi
BLOCK
WRITE
CONTROL
LOGIC
CLK
CKE
CS
MASK
WRITE
MASK
REGISTER
COLOR
REGISTER
INPUT BUFFER
CONTROL
LOGIC
MUX
•
COLUMN
MASK
DQMi
DQi
(i=0~31)
TIMING REGISTER
SENSE
AMPLIFIER
RAS
CAS
WE
DSF
DQMi
•
256Kx32
CELL
ARRAY
256Kx32
CELL
ARRAY
ROW DECORDER
BANK SELECTION
•
SERIAL
COUNTER
COLUMN ADDRESS
BUFFER
ROW ADDRESS
BUFFER
REFRESH
COUNTER
ADDRESS REGISTER
CLOCK ADDRESS(A
0
~A
10
)
* Samsung Electronics reserves the right to
change products or specification without
notice.
-3-
OUTPUT BUFFER
LATENCY &
BURST LENGTH
PROGRAMING
REGISTER
COLUMN
DECORDER
Rev. 1.2 (Jul. 1999)
KM4132G512A
PIN CONFIGURATION
(TOP VIEW)
D 1
D 1
V
S
D 9
Q
V
D
NC
DQM3
DQM1
CLK
CKE
DSF
N.C
A
9 A
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
2
D
2
2
2
2
1
1
D
1
1
S
S
D
S
DQ29
V
SSQ
DQ30
DQ31
V
SS
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
V
DD
DQ0
DQ1
V
SSQ
DQ2
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
8
7
7
7
7
7
7
7
7
7
7
6
6
6
6
6
6
6
6
6
6
5
5
5
5
5
5
5
5
5
D
V
D
D
V
D
D
V
D
D
V
D
D
V
V
D
A
A
A
A
V
N.C
N.C
N.C
N.C
N.C
V
A
A
A
1
A
0
*PQFP (Height = 3.0mmMAX)
Forward Type
mm
2
0.65
2
4
6
8
DQ3
V
DDQ
DQ4
DQ5
V
S
D 6
Q
V
D
D 1
D 1
V
S
D 1
D 1
V
D
V
D
PIN CONFIGURATION DESCRIPTION
Name
CLK
CS
System Clock
Chip Select
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQMi
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / Column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA , Column address : CA ~ CA
Selects bank to be activated during row address latch time.
Latches row addresses on the positive going edge of the CLK with
Latches column addresses on the positive going edge of the CLK with
Enables write operation and Row precharge.
CAS WE
Makes data output Hi-Z, t
after the clock and masks the output.
low.
low.
CKE
Clock Enable
A
0
~ A
9
BA(A )
RAS
CAS
WE
DQMi
DQi
Address
Data inputs/outputs are multiplexed on the same pins.
Define Special Function
/V
/V
Power Supply /Ground
Data Output Power /Ground
No Connection
immunity.
V
V
D 2
D 2
V
S
D 2
D 2
V
D
D M
D M
W
C S
A
C
B (
1
)
S
8
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
3
-4-
Rev. 1.2 (Jul. 1999)
KM4132G512A
ABSOLUTE MAXIMUM RATINGS
(Voltage referenced to V
SS
)
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0
~
4.6
-1.0
~
4.6
-55 ~ +150
1
50
CMOS SGRAM
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V)
Parameter
Supply voltage
Input high voltage
Input low voltage
Output high voltage
Output low voltage
Input leakage current
Output leakage current
Output Loading Condition
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
LI
I
LO
Min
3.0
2.0
-0.3
2.4
-
-10
-10
Typ
3.3
3.0
0
-
-
-
-
Max
3.6
V
DDQ
+0.3
0.8
-
0.4
10
10
see figure 1
Unit
V
V
V
V
V
uA
uA
Note
5
1
2
I
OH
= -2mA
I
OL
= 2mA
3
4
Note :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. Dout is disabled, 0V
≤
V
OUT
≤
V
DD.
5. The VDD condition of KM4132G512A-5/C/6 is 3.135V~3.6V.
CAPACITANCE
(V
DD
/V
DDQ
= 3.3V, T
A
= 23°C, f = 1MHz)
Pin
Clock
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
-
-
-
-
Max
4.0
4.0
4.0
5.0
Unit
pF
pF
pF
pF
RAS, CAS, WE, CS, CKE, DQM
i
,DSF
Address
DQ
i
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Decoupling Capacitance between V
DD
and V
SS
Decoupling Capacitance between V
DDQ
and V
SSQ
Symbol
C
DC1
C
DC2
Value
0.1 + 0.01
0.1 + 0.01
Unit
uF
uF
Note :
1. V
DD
and V
DDQ
pins are separated each other.
All V
DD
pins are connected in chip. All V
DDQ
pins are connected in chip.
2. V
SS
and V
SSQ
pins are separated each other
All V
SS
pins are connected in chip. All V
SSQ
pins are connected in chip.
-5-
Rev. 1.2 (Jul. 1999)
ADI 工业技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
