KM68V512B, KM68U512B Family
Document Title
64Kx8 bit Low Power and Low Voltage CMOS Static RAM
CMOS SRAM
Revision History
Revision No.
0
1.0
History
Design target
Finalize
Draft Data
November 25, 1997
August 27, 1998
Remark
Advance
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 1.0
August 1998
KM68V512B, KM68U512B Family
64Kx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
•
Process Technology : TFT
•
Organization : 64Kx8
•
Power Supply Voltage
KM68V512A family : 3.0~3.6V
KM68U512A family : 2.7~3.3V
•
Low Data Retention Voltage : 2V(Min)
•
Three state output and TTL Compatible
•
Package Type : 32-TSOP1-0820F, 32-TSOP1-0813.4F
CMOS SRAM
GENERAL DESCRIPTION
The KM68V512B and KM68U512B families are fabricated
by SAMSUNG′s advanced CMOS process technology. The
families support various operating temperature ranges and
has various package types for user flexibility of system
design. The family also support low data retention voltage
for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
Operating
Temperature
V
CC
Range
Speed (ns)
Standby
(Isb
1
, Max)
Operating
(Icc
2
, Max)
30mA
25mA
85
1)
/100ns
KM68V512BLI-L
Industrial(-40~85°C)
KM68U512BLI-L
1. The parameter is measured with 30pF test load.
PKG Type
KM68V512BL-L
Commercial(0~70°C)
KM68U512BL-L
3.0 ~ 3.6V
2.7 ~ 3.3V
10µA
3.0 ~ 3.6V
2.7 ~ 3.3V
30mA
25mA
32-TSOP1-F
32-sTSOP1-F
PIN DESCRIPTION
A11
A9
A8
A13
WE
CS2
A15
VCC
N.C
N.C
A14
A12
A7
A6
A5
A4
A11
A9
A8
A13
WE
CS2
A15
VCC
N.C
N.C
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
A4
A5
A6
A7
A8
A12
A13
A14
A15
32-
S
TSOP
TYPE1 - Forward
Row
select
Memory array
512 rows
128×8 columns
32-TSOP
Type1 - Forward
I/O
1
I/O
8
Data
cont
I/O Circuit
Column select
Data
cont
Name
Function
Name
Function
CS1
CS2
WE
OE
A0
A1
A2
A3 A9 A10 A11
CS
1
,CS
2
Chip Select Inputs
OE
WE
A
0
~A
15
Output Enable
Write Enable Input
Address Inputs
I/O
1
~I/O
8
Data Inputs/Outputs
Vcc
Vss
N.C
Power
Ground
No Connection
Control
logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
Revision 1.0
August 1998
2
KM68V512B, KM68U512B Family
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Part Name
KM68V512BLT-8L
KM68V512BLT-10L
KM68U512BLT-8L
KM68U512BLT-10L
Function
32-TSOP1 F, 85ns, 3.3V, LL
32-TSOP1 F, 100ns, 3.3V, LL
32-TSOP1 F, 85ns, 3.0V, LL
32-TSOP1 F, 100ns, 3.0V, LL
CMOS SRAM
Industrial Temperature Products(-40~85°C)
Part Name
KM68V512BLTI-8L
KM68V512BLTI-10L
KM68V512BLTGI-8L
KM68V512BLTGI-10L
KM68U512BLTI-8L
KM68U512BLTI-10L
KM68U512BLTGI-8L
KM68U512BLTGI-10L
Function
32-TSOP1 F, 85ns, 3.3V, LL
32-TSOP1 F, 100ns, 3.3V, LL
32-sTSOP1 F, 85ns,3.3V,LL
32-sTSOP1 F, 100ns,3.3V,LL
32-TSOP1 F, 85ns, 3.0V, LL
32-TSOP1 F, 100ns, 3.0V, LL
32-sTSOP1 F, 85ns, 3.0V, LL
32-sTSOP1 F, 100ns,3.0V, LL
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
L
L
L
CS
2
X
1)
L
H
H
H
OE
X
1)
X
1)
H
L
X
1)
WE
X
1)
X
1)
H
H
L
I/O
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disabled
Read
Write
Power
Standby
Standby
Active
Active
Active
1. X means don′t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Soldering temperature and time
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
T
SOLDER
Ratings
-0.5 to V
CC
+0.5
-0.3 to 4.6
1
-65 to 150
0 to 70
-40 to 85
260°C, 10sec (Lead Only)
Unit
V
V
W
°C
°C
°C
-
Remark
-
-
-
-
KM68V512BL, KM68U512BL
KM68V512BLI, KM68U512BLI
-
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 1.0
August 1998
KM68V512B, KM68U512B Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Product
KM68V512B Family
KM68U512B Family
All Family
KM68V512B, KM68U512B Family
KM68V512B, KM68U512B Family
Min
3.0
2.7
0
2.2
-0.3
3)
Typ
3.3
3.0
0
-
-
CMOS SRAM
Max
3.6
3.3
0
Vcc+0.3V
2)
0.6
Unit
V
V
V
V
V
Note:
1. Commercial Product : T
A
=0 to 70°C, otherwise specified
Industrial Product : T
A
=-40 to 85°C, otherwise specified
2. Overshoot : V
CC
+3.0V in case of pulse width
≤
30ns
3. Undershoot : -3.0V in case of pulse width
≤
30ns
4. Overshoot and undershoot are sampled, not 100% tested
CAPACITANCE
1)
(f=1MHz, T
A
=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
6
8
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply
Symbol
I
LI
I
LO
I
CC
I
CC1
Average operating current
I
CC2
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current (CMOS)
V
OL
V
OH
I
SB
I
SB1
Cycle time=Min, 100% duty, I
IO
=0mA
CS
1
=V
IL
, CS
2
=V
IH
, V
IN
=V
IL
or V
IH
I
OL
=2.1mA
I
OH
=-1.0mA
CS
1
=V
IH
, CS
2
=V
IL
, Other inputs=V
IL
or V
IH
CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V,
or CS
2
≤0.2V
,
Other inputs=0~Vcc
Test Conditions
V
IN
=Vss to Vcc
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL,
Read
Cycle time=1µs, 100% duty, I
IO
=0mA,
CS
1
≤0.2V,
CS
2
≥Vcc-0.2V,
V
IN
≤0.2V
or V
IN
≥Vcc-0.2V
KM68V512B
KM68U512B
Min
-1
-1
-
-
-
-
-
2.4
-
-
Typ
-
-
-
-
-
-
-
-
-
-
Max
1
1
5
5
30
25
0.4
-
0.3
10
Unit
µA
µA
mA
mA
mA
mA
V
V
mA
µA
4
Revision 1.0
August 1998
KM68V512B, KM68U512B Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :C
L
1)
=100pF+1TTL
1. 85ns part tested with 30pF test load.
CMOS SRAM
C
L
*
* Including scope and jig capacitance
AC CHARACTERISTICS
(KM68V512B Family:Vcc=3.0~3.6V, KM68U512B Family:Vcc=2.7~3.3V,
Commercial products:T
A
=0 to 70°C, Industrial products:T
A
=-40 to 85°C
)
Speed Bins
Parameter List
Symbol
Min
85ns
Max
-
85
85
45
-
-
30
20
-
-
-
-
-
-
-
-
25
-
-
-
Min
100
-
-
-
10
5
0
0
15
100
80
0
80
70
0
0
0
40
0
5
100ns
Max
-
100
100
50
-
-
30
20
-
-
-
-
-
-
-
-
30
-
-
-
Units
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write pulse width
Write
Write recovery time
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WR1
t
WHZ
t
DW
t
DH
t
OW
85
-
-
-
10
5
0
0
10
85
70
0
70
60
0
0
0
35
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Sym
V
DR
I
DR
t
SDR
t
RDR
Test Condition
CS
1
≥Vcc-2.0V,
CS
2
≥Vcc-2.0V
or CS
2
≤0.2V
Vcc=3.0V, CS
1
≤Vcc-0.2V,
CS
2
≥Vcc-0.2V
or CS
2
≤0.2V
See data retention waveform
Min
2.0
-
0
5
Typ
-
-
-
-
Max
3.6
10
-
-
Unit
V
µA
ms
5
Revision 1.0
August 1998
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