Datasheet> 器件分类 > 嵌入式处理器和控制器> 微控制器和处理器> TS87C51RD2ELR

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TS87C51RD2ELR: 产品描述Microcontroller, 8-Bit, OTPROM, CMOS, PQCC68, PLASTIC, LCC-68; 产品类别嵌入式处理器和控制器微控制器和处理器; 文件大小699KB，共72页; 制造商TEMIC; 官网地址http://www.temic.de/

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TS87C51RD2ELR概述

Microcontroller, 8-Bit, OTPROM, CMOS, PQCC68, PLASTIC, LCC-68

TS87C51RD2ELR规格参数

参数名称	属性值
厂商名称	TEMIC
包装说明	PLASTIC, LCC-68
Reach Compliance Code	unknown
具有ADC	NO
地址总线宽度	16
位大小	8
DAC 通道	NO
DMA 通道	NO
外部数据总线宽度	8
JESD-30 代码	S-PQCC-J68
I/O 线路数量	48
端子数量	68
PWM 通道	YES
封装主体材料	PLASTIC/EPOXY
封装形状	SQUARE
封装形式	CHIP CARRIER
认证状态	Not Qualified
ROM可编程性	OTPROM
表面贴装	YES
技术	CMOS
端子形式	J BEND
端子位置	QUAD
uPs/uCs/外围集成电路类型	MICROCONTROLLER

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TS80C51RA2/RD2

TS83C51RB2/RC2/RD2

TS87C51RB2/RC2/RD2

8-bit CMOS Microcontroller 0-60 MHz

1. Description

TEMIC TS80C51Rx2 is high performance CMOS ROM,

OTP, EPROM and ROMless versions of the 80C51

CMOS single chip 8-bit microcontroller.

The TS80C51Rx2 retains all features of the TEMIC

80C51 with extended ROM/EPROM capacity (16/32/64

Kbytes), 256 bytes of internal RAM, a 7-source , 4-level

interrupt system, an on-chip oscilator and three timer/

counters.

In addition, the TS80C51Rx2 has a Programmable

Counter Array, an XRAM of 256 or 768 bytes, a

Hardware Watchdog Timer, a more versatile serial

channel that facilitates multiprocessor communication

(EUART) and a X2 speed improvement mechanism.

The fully static design of the TS80C51Rx2 allows to

reduce system power consumption by bringing the clock

frequency down to any value, even DC, without loss of

data.

The TS80C51Rx2 has 2 software-selectable modes of

reduced activity for further reduction in power

consumption. In the idle mode the CPU is frozen while

the timers, the serial port and the interrupt system are still

operating. In the power-down mode the RAM is saved

and all other functions are inoperative.

2. Features

80C52 Compatible

•

8051 pin and instruction compatible

•

Four 8-bit I/O ports

•

Three 16-bit timer/counters

•

256 bytes scratchpad RAM

Hardware Watchdog Timer (One-time enabled with

Reset-Out)

2 extra 8-bit I/O ports available on RD2 with high

pin count packages

Asynchronous port reset

Interrupt Structure with

•

7 Interrupt sources,

•

4 level priority interrupt system

High-Speed Architecture

•

40 MHz @ 5V, 30MHz @ 3V

•

X2 Speed Improvement capability (6 clocks/

machine cycle)

30 MHz @ 5V, 20 MHz @ 3V (Equivalent to

60 MHz @ 5V, 40 MHz @ 3V)

Full duplex Enhanced UART

•

Framing error detection

•

Automatic address recognition

Dual Data Pointer

On-chip ROM/EPROM (16K-bytes, 32K-bytes, 64K-

bytes)

On-chip eXpanded RAM (XRAM) (256 or 768 bytes)

Programmable Clock Out and Up/Down Timer/

Counter 2

Programmable Counter Array with

•

High Speed Output,

•

Compare / Capture,

•

Pulse Width Modulator,

•

Watchdog Timer Capabilities

Low EMI (inhibit ALE)

Power Control modes

•

Idle mode

•

Power-down mode

•

Power-off Flag

Once mode (On-chip Emulation)

Power supply: 4.5-5V, 2.7-5.5V

Temperature ranges: Commercial (0 to 70

C) and

Industrial (-40 to 85

Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44

(window), CDIL40 (window), PLCC68, VQFP64

1.4, JLCC68 (window)

Rev. B - Aug. 24, 1999

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