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KM44S32030AN-G

产品描述Synchronous DRAM, 32MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54
产品类别存储    存储   
文件大小102KB,共10页
制造商SAMSUNG(三星)
官网地址http://www.samsung.com/Products/Semiconductor/
下载文档 详细参数 选型对比 全文预览

KM44S32030AN-G概述

Synchronous DRAM, 32MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54

KM44S32030AN-G规格参数

参数名称属性值
厂商名称SAMSUNG(三星)
零件包装代码TSOP2
包装说明TSOP,
针数54
Reach Compliance Codeunknown
ECCN代码EAR99
访问模式FOUR BANK PAGE BURST
最长访问时间5.4 ns
JESD-30 代码R-PDSO-G54
长度11.2 mm
内存密度134217728 bit
内存集成电路类型SYNCHRONOUS DRAM
内存宽度4
功能数量1
端口数量1
端子数量54
字数33554432 words
字数代码32000000
工作模式SYNCHRONOUS
最高工作温度70 °C
最低工作温度
组织32MX4
封装主体材料PLASTIC/EPOXY
封装代码TSOP
封装形状RECTANGULAR
封装形式SMALL OUTLINE, THIN PROFILE
认证状态Not Qualified
座面最大高度1.2 mm
最大供电电压 (Vsup)3.6 V
最小供电电压 (Vsup)3 V
标称供电电压 (Vsup)3.3 V
表面贴装YES
技术CMOS
温度等级COMMERCIAL
端子形式GULL WING
端子节距0.4 mm
端子位置DUAL
宽度10.16 mm

KM44S32030AN-G文档预览

shrink-TSOP
KM44S32030AN
Preliminary
CMOS SDRAM
128Mb SDRAM
Shrink TSOP
8M x 4Bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 0.1
April 1999
Samsung Electronics reserves the right to change products or specification without notice.
REV. 0.1 Apr. 1999
shrink-TSOP
KM44S32030AN
Revision History
Version 0.0 (April 21. 1999,
Preliminary)
• Preliminary specification for shrink-TSOP(STSOP).
• Based on the standard TSOP-II specification(KM44S32030AT, Rev. 0.0, April 19. 1999).
Preliminary
CMOS SDRAM
Version 0.1 (April 22. 1999,
Preliminary)
• Changed package length from 11.00mm to 11.20mm in the page of
PACKAGE DIMENSIONS.
REV. 0.1 Apr. 1999
shrink-TSOP
KM44S32030AN
Preliminary
CMOS SDRAM
8M x 4Bit x 4 Banks Synchronous DRAM in New Shrink-TSOP(sTSOP)
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
- CAS latency (2 & 3)
- Burst length (1, 2, 4, 8 & Full page )
- Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K Cycle)
GENERAL DESCRIPTION
The
KM44S32030
AN is 134,217,728 bits synchronous high
data rate Dynamic RAM organized as 4 x 8,388,608 words by 4
bits, fabricated with SAMSUNG′s high performance CMOS
technology. Synchronous design allows precise cycle control
with the use of system clock I/O transactions are possible on
every clock cycle. Range of operating frequencies, programma-
ble burst length and programmable latencies allow the same
device to be useful for a variety of high bandwidth, high perfor-
mance memory system applications.
ORDERING INFORMATION
Part No.
Max Freq.
Interface Package
54pin
sTSOP
KM44S32030AN-G/FA 133MHz(CL=3)
KM44S32030AN-G/F8 125MHz(CL=3)
KM44S32030AN-G/FH 100MHz(CL=2)
KM44S32030AN-G/FL 100MHz(CL=3)
LVTTL
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
Data Input Register
LDQM
Bank Select
8M x 4
Sense AMP
8M x 4
8M x 4
8M x 4
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Programming Register
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
*
Samsung Electronics reserves the right to change products or specification without notice.
REV. 0.1 Apr. 1999
shrink-TSOP
KM44S32030AN
PIN CONFIGURATION
(Top view)
V
DD
N.C
V
DDQ
N.C
DQ0
V
SSQ
N.C
N.C
V
DDQ
N.C
DQ1
V
SSQ
N.C
V
DD
N.C
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
Preliminary
CMOS SDRAM
54Pin sTSOP
(400mil x 441mil)
(0.4 mm Pin pitch)
V
SS
N.C
V
SSQ
N.C
DQ3
V
DDQ
N.C
N.C
V
SSQ
N.C
DQ2
V
DDQ
N.C
V
SS
N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
V
SS
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
11
, Column address : CA
0
~ CA
9
, CA
11
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
CKE
Clock enable
A
0
~ A
11
BA
0
~ BA
1
RAS
CAS
WE
DQM
DQ
0
~
3
V
DD
/V
SS
V
DDQ
/V
SSQ
N.C/RFU
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Power supply/ground
Data output power/ground
No connection
/reserved for future use
REV. 0.1 Apr. 1999
shrink-TSOP
KM44S32030AN
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
Preliminary
CMOS SDRAM
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (voltage referenced to V
SS
= 0V, T
A
= 0 to 70°C)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
LI
Min
3.0
2.0
-0.3
2.4
-
-10
Typ
3.3
3.0
0
-
-
-
Max
3.6
V
DD
+0.3
0.8
-
0.4
10
Unit
V
V
V
V
V
uA
1
2
I
OH
= -2mA
I
OL
= 2mA
3
Note
Notes :
1. V
IH
(max) = 5.6V AC.The overshoot voltage duration is
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
3ns.
3. Any input 0V
V
IN
V
DDQ
,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
Clock
(V
DD
= 3.3V, T
A
= 23°C, f = 1MHz, V
REF
=1.4V
±
200 mV)
Pin
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2.5
2.5
2.5
4.0
Max
4.0
5.0
5.0
6.5
Unit
pF
pF
pF
pF
Note
1
2
2
3
RAS, CAS, WE, CS, CKE, DQM
Address
DQ
0
~ DQ
3
Notes :
1. -A only specify a maximum value of 3.5pF
2. -A only specify a maximum value of 3.8pF
3. -A only specify a maximum value of 6.0pF
REV. 0.1 Apr. 1999

KM44S32030AN-G相似产品对比

KM44S32030AN-G KM44S32030AN-FA KM44S32030AN-FL KM44S32030AN-F8 KM44S32030AN-FH
描述 Synchronous DRAM, 32MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54 Synchronous DRAM, 32MX4, 5.4ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54 Synchronous DRAM, 32MX4, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54 Synchronous DRAM, 32MX4, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54 Synchronous DRAM, 32MX4, 6ns, CMOS, PDSO54, 0.400 X 0.441 INCH, 0.40 MM PITCH, STSOP2-54
厂商名称 SAMSUNG(三星) SAMSUNG(三星) SAMSUNG(三星) SAMSUNG(三星) SAMSUNG(三星)
零件包装代码 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2
包装说明 TSOP, TSOP, TSOP, TSOP, TSOP,
针数 54 54 54 54 54
Reach Compliance Code unknown unknown unknown unknown unknown
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99
访问模式 FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST
最长访问时间 5.4 ns 5.4 ns 6 ns 6 ns 6 ns
JESD-30 代码 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54 R-PDSO-G54
长度 11.2 mm 11.2 mm 11.2 mm 11.2 mm 11.2 mm
内存密度 134217728 bit 134217728 bit 134217728 bit 134217728 bit 134217728 bit
内存集成电路类型 SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM
内存宽度 4 4 4 4 4
功能数量 1 1 1 1 1
端口数量 1 1 1 1 1
端子数量 54 54 54 54 54
字数 33554432 words 33554432 words 33554432 words 33554432 words 33554432 words
字数代码 32000000 32000000 32000000 32000000 32000000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 70 °C 70 °C 70 °C 70 °C 70 °C
组织 32MX4 32MX4 32MX4 32MX4 32MX4
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSOP TSOP TSOP TSOP TSOP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm
最大供电电压 (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
最小供电电压 (Vsup) 3 V 3 V 3 V 3 V 3 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING
端子节距 0.4 mm 0.4 mm 0.4 mm 0.4 mm 0.4 mm
端子位置 DUAL DUAL DUAL DUAL DUAL
宽度 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm
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