256Kx4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating).
CMOS SRAM
Revision History
Rev. No.
Rev. 0.0
Rev. 1.0
History
Initial release with Preliminary.
Release to Final Data Sheet.
1.1. Delete Preliminary.
1.2. Relax DC characteristics.
Item
I
CC
12ns
15ns
20ns
Add 10ns & Low Power Ver.
Preliminary
CCPCCCRCELIMINARY
Draft Data
Aug. 5th. 1998
Sep. 7th. 1998
Remark
Preliminary
Final
Previous
65mA
63mA
60mA
Changed
70mA
68mA
65mA
Apr. 24. 2000
Final
Rev. 2.0
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Revision 2.0
April 2000
PRELIMINARY
PRELIMINARY
KM64V1003C/CL, KM64V1003CI/CLI
FEATURES
• Fast Access Time 10,12,15,20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 30mA(Max.)
(CMOS) : 5mA(Max.)
0.5mA(Max.) L-Ver. only
Operating KM64V1003C/CL-10 : 75mA(Max.)
KM64V1003C/CL-12 : 70mA(Max.)
KM64V1003C/CL-15 : 68mA(Max.)
KM64V1003C/CL-20 : 65mA(Max.)
• Single 3.3±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention ; L-ver. Only
• Center Power/Ground Pin Configuration
• Standard Pin Configuration :
KM64V1003CJ : 32-SOJ-400
CMOS SRAM
256K x 4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating)
GENERAL DESCRIPTION
Preliminary
CCPCCCRCELIMINARY
The KM64V1003C is a 1,048,576-bit high-speed Static Ran-
dom Access Memory organized as 262,144 words by 4 bits.
The KM64V1003C uses 4 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using SAM-
SUNG′s advanced CMOS process and designed for high-
speed circuit technology. It is particularly well suited for use in
high-density
high-speed
system
applications.
The
KM64V1003C is packaged in a 400 mil 32-pin plastic SOJ.
ORDERING INFORMATION
KM64V1003C/CL-10/12/15/20
KM64V1003CI/CLI-10/12/15/20
Commercial Temp.
Industrial Temp.
PIN CONFIGURATION
(Top View)
N.C
1
2
3
4
5
6
7
8
9
32 A
17
31 A
16
30 A
15
29 A
14
28 A
13
27
OE
FUNCTIONAL BLOCK DIAGRAM
A
0
A
1
A
2
A
3
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
Pre-Charge Circuit
CS
I/O
1
Vcc
26 I/O
4
SOJ
25 Vss
24 Vcc
23 I/O
3
22 A
12
21 A
11
20 A
10
19
18
A
9
A
8
Row Select
Vss
Memory Array
512 Rows
512x4 Columns
I/O
2
10
WE
A
4
A
5
A
6
11
12
13
14
15
I/O
1
~ I/O
4
Data
Cont.
CLK
Gen.
I/O Circuit &
Column Select
A
7
N.C 16
17 N.C
PIN FUNCTION
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
A
17
Pin Name
A
0
- A
17
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Data Inputs/Outputs
Power(+3.3V)
Ground
No Connection
CS
WE
OE
WE
CS
OE
I/O
1
~ I/O
4
V
CC
V
SS
N.C
-2-
Revision 2.0
April 2000
PRELIMINARY
PRELIMINARY
KM64V1003C/CL, KM64V1003CI/CLI
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
CC
CMOS SRAM
Rating
-0.5 to 4.6
Unit
V
V
W
°C
°C
°C
V
-0.5 to 4.6
Preliminary
CCPCCCRCELIMINARY
P
d
1
T
STG
T
A
T
A
-65 to 150
0 to 70
-40 to 85
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.2
-0.5*
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.5**
0.8
Unit
V
V
V
V
* V
IL
(Min) = -2.0V a.c (Pulse Width
≤
8ns) for I
≤
20mA.
** V
IH
(Max) = V
CC
+ 2.0V a.c (Pulse Width
≤
8ns) for I
≤
20mA.
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
Test Conditions
V
IN
= V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
10ns
12ns
15ns
20ns
Standby Current
I
SB
I
SB1
Min. Cycle, CS=V
IH
f=0MHz, CS
≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
Normal
L-ver.
Min
-2
-2
-
-
-
-
-
-
-
-
2.4
Max
2
2
75
70
68
65
30
5
0.5
0.4
-
V
V
mA
mA
Unit
µA
µA
mA
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
6
Unit
pF
pF
-3-
Revision 2.0
April 2000
PRELIMINARY
PRELIMINARY
KM64V1003C/CL, KM64V1003CI/CLI
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
Value
0V to 3V
Preliminary
CCPCCCRCELIMINARY
3ns
1.5V
See below
CMOS SRAM
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
R
L
= 50Ω
+3.3V
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
D
OUT
319Ω
353
Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
KM64V1003C-10
KM64V1003C-12
KM64V1003C-15
KM64V1003C-20
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address
Chip Selection to Power Up Time
Chip Selection to Power Down-
Symbol
t
RC
t
AA
t
CO
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
PU
t
PD
Min
10
-
-
-
3
0
0
0
3
0
-
Max
-
10
10
5
-
-
5
5
-
-
10
Min
12
-
-
-
3
0
0
0
3
0
-
Max
-
12
12
6
-
-
6
6
-
-
12
Min
15
-
-
-
3
0
0
0
3
0
-
Max
-
15
15
7
-
-
7
7
-
-
15
Min
20
-
-
-
3
0
0
0
3
0
-
Max
-
20
20
9
-
-
9
9
-
-
20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
-4-
Revision 2.0
April 2000
PRELIMINARY
PRELIMINARY
KM64V1003C/CL, KM64V1003CI/CLI
WRITE CYCLE*
KM64V1003C-10
KM64V1003C-12
KM64V1003C-15
KM64V1003C-20
CMOS SRAM
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
WR
t
WHZ
t
DW
t
DH
t
OW
Min
10
7
0
7
7
10
0
0
5
0
3
Max
-
-
-
-
-
-
-
5
-
-
-
Min
Max
Min
Max
Min
Max
-
-
-
-
-
-
-
9
-
-
-
12
-
15
-
20
Preliminary
CCPCCCRCELIMINARY
8
-
9
-
10
0
8
8
12
0
0
6
0
3
-
-
-
-
-
6
-
-
-
0
9
9
15
0
0
7
0
3
-
-
-
-
-
7
-
-
-
0
10
10
20
0
0
8
0
3
* The above parameters are also guaranteed at industrial temperature range.
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