ADVANCE
QUANTUM DEVICES, INC.
MT28SF161
1 MEG x 16, 2 MEG x 8 FLASH MEMORY
FLASH MEMORY
FEATURES
•
•
•
•
Thirty-two 64KB/(32K-word) erase blocks
Programmable sector lock
Deep Power-Down Mode: 5µA MAX
3V SmartVoltage* Technology (SVT):
2.7V to 3.6V V
CC
3.3V
±0.3V
or 5V
±
5% V
PP
Address access times: 80ns, 100ns, 150ns
Selectable organizations: 1,048,576 x 16 or
2,097,152 x 8
Industry-standard pinouts
Inputs and outputs are fully TTL-compatible
Automated write and erase algorithm
Byte- or word-wide read and write
1 MEG x 16, 2 MEG x 8
3V S
MART
V
OLTAGE
, SECTORED ERASE
PIN ASSIGNMENT (Top View)
56-Pin TSOP Type I
(FB-3)
NC
CE1
NC
A20
A19
A18
A17
A16
Vcc
A15
A14
A13
A12
CE0
V
PP
RP
A11
A10
A9
A8
Vss
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
WP
WE
OE
RY/BY
DQ15
DQ7
DQ14
DQ6
Vss
DQ13
DQ5
DQ12
DQ4
Vcc
Vss
DQ11
DQ3
DQ10
DQ2
Vcc
DQ9
DQ1
DQ8
DQ0
A0
BYTE
NC
NC
•
•
•
•
•
•
OPTIONS
• Timing
80ns access
100ns access
150ns access
MARKING
-8
-10
-15
• Packages
Plastic 56L TSOP Type 1 (14 x 20mm)
VG
• Part Number Example: MT28SF161VG-8
GENERAL DESCRIPTION
The MT28SF161 is a nonvolatile, electrically block-
erasable (Flash), programmable read-only memory con-
taining 16,777,216 bits organized as 1,048,576 words by 16
bits or 2,097,152 words by 8 bits. SmartVoltage Technology
(SVT) provides industry standard, multi- or single-voltage,
dual supply operation. Writing or erasing the device is
done with either a 3.3V or 5V V
PP
voltage, while all opera-
tions are performed with a 3.0V V
CC
. It is fabricated with
Micron’s advanced CMOS floating-gate process.
The MT28SF161 is organized into 32 separately erasable
blocks. To ensure that critical data is protected from
accidental erasure or overwrite, the MT28SF161 features
independently hardware-lockable blocks. Writing or erasing
a protected block requires driving
?
W
/
P HIGH in addition to
MT28SF161
F14.pm5 – Rev. 9/95
executing the normal write or erase sequences. Any
unprotected block is written and erased with no additional
security measures.
In addition to status register polling, the MT28SF161
provides a READY/?B
?
U
/
SY (RY/?B
/
Y) output to indicate write
/
and erase completion. Operations are executed by issuing
commands from an industry standard command set.
The byte or word address is issued to read the memory
array with
?
C
/
E
/
0,
?
C
/
E
/
1 and
?
O
/
E LOW and
?
W
/
E HIGH. Valid
data is output until the next address is issued. The
?
B
?
Y
?
T
/
E pin
is used to switch the data path between 8 bits wide and 16
bits wide. When
?
B
?
Y
?
T
/
E is LOW, data is output on DQ0 - DQ7
while DQ8 -DQ15 are High-Z. When
?
B
?
Y
?
T
/
E is HIGH, data is
output on DQ0 - DQ15.
1
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Quantum Devices, Inc.
*All registered and unregistered trademarks are the sole property of their respective companies.
MT28SF161
F14.pm5 – Rev. 9/95
QUANTUM DEVICES, INC.
FUNCTIONAL BLOCK DIAGRAM
8
Input
Buffer
BYTE
I/O
Control
8
Input
Buffer
Logic
Addr.
Buffer/
Latch
11
21
10
A0 - A20
64KB Memory Block (0)
64KB Memory Block (1)
64KB Memory Block (2)
Addr.
Counter
Power
(Current)
Control
X - Decoder / Block Erase Control
MT28SF161
1 MEG x 16, 2 MEG x 8 FLASH MEMORY
2
State
Machine
Y-
Decoder
Y - Select Gates
64KB Memory Block (29)
64KB Memory Block (30)
64KB Memory Block (31)
Logic
V
PP
Switch/
Pump
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
Block Status
Register
Status
Register
Identification
Register
8
8
8
Input Data
Latch/Mux
WP
16
DQ8 - DQ15
Command
Execution
CE0
CE1
OE
WE
8
DQ0 - DQ7
8
RP
Vcc
RY/BY
V
PP
Output
Buffer
Output
Buffer
MUX
ADVANCE
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Quantum Devices, Inc.
ADVANCE
QUANTUM DEVICES, INC.
MT28SF161
1 MEG x 16, 2 MEG x 8 FLASH MEMORY
PIN DESCRIPTIONS
TSOP PIN
NUMBERS
55
SYMBOL
?
W
/
E
TYPE
Input
DESCRIPTION
Write Enable: Determines if a given cycle is a write cycle. If
?
W
/
E is LOW,
the cycle is either a write to the Command Execution Logic (CEL) or to the
memory array.
Write Protect: Unlocks all protected blocks when HIGH if V
PP
=
V
PPH
1
(3.3V) or V
PPH
2
(5V) during a write or erase. Does not affect write or erase
operation on other blocks.
Chip Enable: Activates the device when LOW at same time as
?
C
/
E
/
1. When
either
?
C
/
E
/
0 or
?
C
/
E
/
1 is HIGH, the device is disabled and goes into standby
power mode.
Chip Enable: Activates the device when LOW at same time as
?
C
/
E
/
0. When
either
?
C
/
E
/
0 or
?
C
/
E
/
1 is HIGH, the device is disabled and goes into standby
power mode.
Reset Power-Down: Clears the status register, sets the Internal State
Machine (ISM) to the array read mode, and places the device in deep
?
power-down mode when LOW. All inputs, including
?
C
/
E
/
0 and C
/
E
/
1, are
“don’t care” and all outputs are High-Z. Must be held HIGH during all other
modes of operation.
Output Enable: Enables data output buffers when LOW. When
?
O
/
E is HIGH,
the output buffers are disabled.
Byte Enable: If
/
B
/
Y
/
T
/
E=HIGH the upper byte is active through DQ8-DQ15. If
/
B
/
Y
/
T
/
E=LOW, DQ8-DQ15 are High-Z, and all data is accessed through
DQ0-DQ7.
Address Inputs: Selects a unique, 16-bit word out of the 1,048,576
available.
56
?
W
/
P
Input
14
C
/
E
/
0
?
Input
2
?
C
/
E
/
1
Input
16
?
R
/
P
Input
54
31
?
O
/
E
?
B
/
Y
/
T
/
E
Input
Input
28, 27, 26, 25, 24,
23, 22, 20, 19, 18,
17, 13, 12, 11, 10,
8, 7, 6, 5, 4
32
A1-A20
Input
A0
Input
Address Input: Lowest order address input when B
/
Y
/
T
/
E is LOW so that a
?
unique byte out of the 2,097,152 may be selected. Not used when
?
B
/
Y
/
T
/
E is
HIGH.
Open Drain Output: Indicates the status of Internal State Machine. When
RY/?B
/
Y = V
OL
, the ISM is busy processing a command. If RY/?B
/
Y = High-Z,
the ISM is ready to accept a new command. During deep power-down,
device or manufacturer ID read, or erase suspend, RY/?B
/
Y is at High-Z.
Output is always active.
Data I/O: Data output pins during any read operation, or data
input pins during a WRITE. Used to input commands to the CEL
for a command input.
Data I/O: Data output pins during any read operation or data input
pins during a WRITE when B
/
Y
/
T
/
E = HIGH. High-Z when
/
B
/
Y
/
T
/
E is
/
LOW.
53
RY/?B
/
Y
Output
33, 35, 38,
40,44, 46,
49, 51
34, 36, 39,
41, 45, 47,
50, 52
DQ0-DQ7
Input/
Output
Input/
Output
DQ8-DQ15
MT28SF161
F14.pm5 – Rev. 9/95
3
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Quantum Devices, Inc.
ADVANCE
QUANTUM DEVICES, INC.
MT28SF161
1 MEG x 16, 2 MEG x 8 FLASH MEMORY
PIN DESCRIPTIONS
TSOP PIN
NUMBERS
1, 3, 29, 30
15
SYMBOL
NC
V
PP
TYPE
-
Supply
DESCRIPTION
No Connect: These pins may be driven or left unconnected.
Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM until
completion of the write or erase, V
PP
must be at V
PPH
1
(3.3V) or V
PPH
2
(5V).
V
PP
= “don’t care” during all other operations.
Power Supply: +2.7V to 3.6V
Ground
9, 37, 43
21, 42, 48
V
CC
V
SS
Supply
Supply
MT28SF161
F14.pm5 – Rev. 9/95
4
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Quantum Devices, Inc.
ADVANCE
QUANTUM DEVICES, INC.
MT28SF161
1 MEG x 16, 2 MEG x 8 FLASH MEMORY
TRUTH TABLE
1
FUNCTION
Standby
Standby
Standby
Deep Power-Down/Reset
READING
Read (word mode)
Read (byte mode)
Output Disable
ERASE SETUP
ERASE CONFIRM
3
WRITE SETUP
WRITE (word mode)
4
WRITE (byte mode)
4
READ ARRAY
5
ERASE SETUP
ERASE CONFIRM
3
WRITE SETUP
WRITE (word mode)
4
WRITE (byte mode)
4
READ ARRAY
5
DEVICE IDENTIFICATION
6
Manufacturer (word mode)
Manufacturer (byte mode)
Device (word mode)
Device (byte mode)
NOTE:
1.
2.
3.
4.
5.
6.
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
X
X
X
X
H
L
H
L
X
L
X
H
L
X
H
X
X
X
X
X
2CH
2CH
38H
38H
00H
High-Z
66H
High-Z
Z
Z
Z
Z
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
H
X
H
H
X
H
L
X
X
X
X
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
V
PPH
X
V
PPH
V
PPH
X
X
V
PPH
X
V
PPH
V
PPH
X
Data-Out Data-Out
Data-Out High-Z
High-Z
20H
D0H
10H/40H
Data-In
Data-In
FFH
20H
D0H
10H/40H
Data-In
Data-In
FFH
High-Z
X
X
X
Data-In
X
X
X
X
X
Data-In
X
X
Z
Z
Z
Z
Z
→
V
OL
Z
Z
→
V
OL
Z
→
V
OL
Z
Z
Z
→
V
OL
Z
Z
→
V
OL
Z
→
V
OL
Z
?
R
/
P
H
H
H
L
?
C
/
E
/
0
H
L
H
X
?
C
/
E
/
1
L
H
H
X
?
O
/
E
X
X
X
X
?
W
/
E
X
X
X
X
?
W
/
P
?
B
?
Y
/
TE
/
X
X
X
X
X
X
X
X
A0
X
X
X
X
A1
X
X
X
X
V
PP
X
X
X
X
DQ0-DQ7 DQ8-DQ15
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
RY/?
?
B
/
Y
Z
Z
Z
Z
WRITE/ERASE (UNPROTECTED BLOCKS)
2
WRITE/ERASE (PROTECTED BLOCKS)
2
L = V
IL
(LOW), H = V
IH
(HIGH), X = V
IL
or V
IH
(don’t care), Z = High-Z.
V
PPH
= V
PPH
1
= 3.3V or V
PPH
= V
PPH
2
= 5V.
Operation must be preceded by ERASE SETUP command.
Operation must be preceded by WRITE SETUP command.
The READ ARRAY command must be issued before reading the array after writing or erasing.
A1-A20 = V
IL
.
MT28SF161
F14.pm5 – Rev. 9/95
5
Micron Quantum Devices, Inc., reserves the right to change products or specifications without notice.
©1995,
Micron Quantum Devices, Inc.
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