64Kx16 Bit High Speed Static RAM(3.3V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Ranges.
Preliminary
PRELIMINARY
CMOS SRAM
Revision History
Rev No.
Rev. 0.0
Rev. 1.0
History
Initial release with Design Target.
Release to Preliminary Data Sheet.
1.1. Replace Design Target to Preliminary.
Release to Final Data Sheet.
2.1. Delete Preliminary.
2.2. Add Capacitive load of the test environment in A.C test load.
2.3. Change D.C characteristics.
Previous spec.
Changed spec.
Items
(8/10/12ns part)
(8/10/12ns part)
I
CC
200/190/180mA
200/195/190mA
I
SB
30mA
50mA
Change Standby and Data Retention Current for L-ver.
Items
Previous spec.
Changed spec.
I
SB
0.5mA
0.7mA
I
DR
at 3.0V
0.4mA
0.5mA
I
DR
at 2.0V
0.3mA
0.4mA
Draft Data
Apr. 1st, 1997
Jun. 1st, 1997
Remark
Design Target
Preliminary
Rev. 2.0
Feb. 25th, 1998
Final
Rev. 2.1
Aug. 4th, 1998
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Rev 2.1
August 1998
PRELIMINARY
KM616V1002B/BL, KM616V1002BI/BLI
64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
• Fast Access Time 8,10,12ns(Max.)
• Low Power Dissipation
Standby (TTL) : 50mA(Max.)
(CMOS): 5mA(Max.)
0.7mA(Max.) L-Ver. only
Operating KM616V1002B/BL - 8 : 200mA(Max.)
KM616V1002B/BL - 10: 195mA(Max.)
KM616V1002B/BL - 12: 190mA(Max.)
• Single 3.3±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention; L-Ver. only
• Center Power/Ground Pin Configuration
• Data Byte Control: LB: I/O
1
~ I/O
8,
UB: I/O
9
~ I/O
16
• Standard Pin Configuration
KM616V1002BJ: 44-SOJ-400
KM616V1002BT: 44-TSOP2-400F
Preliminary
PRELIMINARY
CMOS SRAM
GENERAL DESCRIPTION
The KM616V1002B is a 1,048,576-bit high-speed Static Ran-
dom Access Memory organized as 65,536 words by 16 bits.
The KM616V1002B uses 16 common input and output lines
and has an output enable pin which operates faster than
address access time at read cycle. Also it allows that lower and
upper byte access by data byte control (UB, LB). The device is
fabricated using SAMSUNG′s advanced CMOS process and
designed for high-speed circuit technology. It is particularly well
suited for use in high-density high-speed system applications.
The KM616V1002B is packaged in a 400mil 44-pin plastic SOJ
or TSOP2 forward.
PIN CONFIGURATION
(Top View)
A
0
A
1
A
2
A
3
A
4
CS
I/O
1
I/O
2
I/O
3
1
2
3
4
5
6
7
8
9
44 A
15
43 A
14
42 A
13
41 OE
40 UB
39 LB
38 I/O
16
37 I/O
15
36 I/O
14
ORDERING INFORMATION
KM616V1002B/BL -8/10/12
KM616V1002BI/BLI -8/10/12
Commercial Temp.
Industrial Temp.
I/O
4
10
Vcc 11
Vss 12
SOJ/
TSOP2
35 I/O
13
34 Vss
33 Vcc
32 I/O
12
31 I/O
11
30 I/O
10
29 I/O
9
28 N.C
27 A
12
26 A
11
25 A
10
24 A
9
23 N.C
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A
0
A
1
I/O
5
13
I/O
6
14
I/O
7
15
I/O
8
16
WE 17
A
5
18
Pre-Charge Circuit
Row Select
A
2
A
3
A
4
A
5
A
6
A
7
I/O
1
~I/O
8
I/O
9
~I/O
16
A
6
19
Memory Array
256 Rows
256x16 Columns
A
7
20
A
8
21
N.C 22
Data
Cont.
Data
Cont.
Gen.
CLK
I/O Circuit &
Column Select
PIN FUNCTION
Pin Name
A
0
- A
15
WE
CS
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Lower-byte Control(I/O
1
~I/O
8
)
Upper-byte Control(I/O
9
~I/O
16
)
Data Inputs/Outputs
Power(+3.3V)
Ground
No Connection
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
OE
LB
UB
WE
OE
UB
LB
CS
I/O
1
~ I/O
16
V
CC
V
SS
N.C
-2-
Rev 2.1
August 1998
PRELIMINARY
KM616V1002B/BL, KM616V1002BI/BLI
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
D
T
STG
T
A
T
A
Rating
-0.5 to 4.6
-0.5 to 4.6
1.0
-65 to 150
0 to 70
-40 to 85
Unit
V
V
W
°C
°C
°C
Preliminary
PRELIMINARY
CMOS SRAM
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*
(T
A
=0 to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
3.0
0
2.0
-0.3**
Typ
3.3
0
-
-
Max
3.6
0
V
CC
+0.3***
0.8
Unit
V
V
V
V
* The above parameters are also guaranteed at industrial temperature range.
** V
IL
(Min) = -2.0V a.c(Pulse Width
≤
6ns) for I
≤
20mA.
*** V
IH
(Max) = V
CC +
2.0V a.c (Pulse Width
≤
6ns) for I
≤
20mA.
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
=V
IH
or V
IL,
I
OUT
=0mA
Min. Cycle, CS=V
IH
f=0MHz, CS≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
Normal
L-Ver.
8ns
10ns
12ns
Standby Current
I
SB
I
SB1
Test Conditions
Min
-2
-2
-
-
-
-
-
-
-
2.4
Max
2
2
200
195
190
50
5
0.7
0.4
-
V
V
mA
mA
Unit
µA
µA
mA
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
* The above parameters are also guaranteed at industrial temperature range.
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
*
Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
6
Unit
pF
pF
-3-
Rev 2.1
August 1998
PRELIMINARY
KM616V1002B/BL, KM616V1002BI/BLI
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
* The above test conditions are also applied at industrial temperature range.
Preliminary
PRELIMINARY
CMOS SRAM
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
R
L
= 50Ω
+3.3V
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
D
OUT
353Ω
319Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
UB, LB Access Time
Chip Enable to Low-Z Output
Output Enable to Low-Z Output
UB, LB Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Hold from Address Change
Sym-
bol
t
RC
t
AA
t
CO
t
OE
t
BA
t
LZ
t
OLZ
t
BLZ
t
HZ
t
OHZ
t
BHZ
t
OH
KM616V1002B/BL-8
Min
8
-
-
-
-
3
0
0
0
0
0
3
Max
-
8
8
4
8
-
-
-
4
4
4
-
KM616V1002B/BL-10
Min
10
-
-
-
-
3
0
0
0
0
0
3
Max
-
10
10
5
10
-
-
-
5
5
5
-
KM616V1002B/BL-12
Min
12
-
-
-
-
3
0
0
0
0
0
3
Max
-
12
12
6
12
-
-
-
6
6
6
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
-4-
Rev 2.1
August 1998
PRELIMINARY
KM616V1002B/BL, KM616V1002BI/BLI
WRITE CYCLE*
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
UB, LB Valid to End of Write
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
BW
t
WR
t
WHZ
t
DW
t
DH
t
OW
KM616V1002B/BL-8
Min
8
6
0
6
6
8
6
0
0
4
0
3
Max
-
-
-
-
-
-
-
-
4
-
-
-
KM616V1002B/BL-10
Min
10
7
0
7
7
10
7
0
0
5
0
3
Max
-
-
-
-
-
-
-
-
5
-
-
-
KM616V1002B/BL-12
Min
12
8
0
8
8
12
8
0
0
6
0
3
Max
-
-
-
-
-
-
-
-
6
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Preliminary
PRELIMINARY
CMOS SRAM
* The above parameters are also guaranteed at industrial temperature range.
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
, UB, LB=V
IL
)
t
RC
Address
t
OH
Data Out
Previous Valid Data
t
AA
Valid Data
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
t
RC
Address
t
AA
t
CO
t
BA
UB, LB
t
BLZ(4,5)
OE
t
OLZ
Data out
High-Z
NOTES(READ
CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or
V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
±200mV
from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
IL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
Logic analyzers are widely used tools in digital design verification and debugging. They can verify the proper functioning of digital circuits and help users identify and troubleshoot faults. They ...[详细]
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