64Kx16 Bit High-Speed CMOS Static RAM(5.0V Operating).
Operated at Commercial and Industrial Temperature Ranges.
CMOS SRAM
Revision History
Rev. No.
Rev. 0.0
Rev. 1.0
History
Initial release with preliminary.
Relax DC characteristics.
Item
I
CC
12ns
15ns
20ns
Add 48-fine pitch BGA.
Changed device part name for FP-BGA.
Item
Previous
Symbol
Z
ex) KM6161002CZ -> KM6161002CF
Changed device ball name for FP-BGA.
Previous
I/O1 ~ I/O8
I/O9 ~ I/O16
Added Data Retention Characteristics.
Draft Data
Aug. 5. 1998
Sep. 7. 1998
Previous
90mA
88mA
85mA
Changed
95mA
93mA
90mA
Sep. 17. 1998
Nov. 5. 1998
Changed
F
Preliminary
Final
Remark
Preliminary
Preliminary
Rev. 2.0
Rev. 2.1
Rev. 2.2
Dec. 10. 1998
Changed
I/O9 ~ I/O16
I/O1 ~ I/O8
Mar. 3. 1999
Final
Rev. 3.0
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions,
please contact the SAMSUNG branch office near your office, call or contact Headquarters.
-1-
Revision 3.0
March 1999
KM6161002C/CL, KM6161002CI/CLI
64K x 16 Bit High-Speed CMOS Static RAM
FEATURES
• Fast Access Time 12,15,20ns(Max.)
• Low Power Dissipation
Standby (TTL)
: 30mA(Max.)
(CMOS) : 5mA(Max.)
0.5mA(Max.) L-ver. only
Operating KM6161002C/CL - 12: 95mA(Max.)
KM6161002C/CL - 15: 93mA(Max.)
KM6161002C/CL - 20: 90mA(Max.)
• Single 5.0V±10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• 2V Minimum Data Retention; L-ver. only
• Center Power/Ground Pin Configuration
• Data Byte Control: LB: I/O
1
~ I/O
8
, UB: I/O
9
~ I/O
16
• Standard Pin Configuration:
KM6161002CJ: 44-SOJ-400
KM6161002CT: 44-TSOP2-400F
KM6161002CF: 48-Fine pitch BGA with 0.75 Ball pitch
CMOS SRAM
GENERAL DESCRIPTION
The KM6161002C is a 1,048,576-bit high-speed Static Random
Access Memory organized as 65,536 words by 16 bits. The
KM6161002C uses 16 common input and output lines and has
at output enable pin which operates faster than address access
time at read cycle. Also it allows that lower and upper byte
access by data byte control (UB, LB). The device is fabricated
using SAMSUNG′s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
KM6161002C is packaged in a 400mil 44-pin plastic SOJ or
TSOP2 forward or 48-Fine pitch BGA.
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
~I/O
8
I/O
9
~I/O
16
ORDERING INFORMATION
KM6161002C/CL -12/15/20
Commercial Temp.
Industrial Temp.
KM6161002CI/CLI -12/15/20
Pre-Charge Circuit
Row Select
Memory Array
512 Rows
128x16 Columns
PIN FUNCTION
Pin Name
Data
Cont.
Data
Cont.
Gen.
CLK
A
9
A
10
A
11
A
12
A
13
A
14
A
15
Pin Function
Address Inputs
Write Enable
Chip Select
Output Enable
Lower-byte Control(I/O
1
~I/O
8
)
Upper-byte Control(I/O
9
~I/O
16
)
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
I/O Circuit &
Column Select
A
0
- A
15
WE
CS
OE
LB
UB
I/O
1
~ I/O
16
WE
OE
UB
LB
CS
V
CC
V
SS
N.C
-2-
Revision 3.0
March 1999
KM6161002C/CL, KM6161002CI/CLI
PIN CONFIGURATION(TOP
VIEW)
1
2
3
CMOS SRAM
4
5
6
A
0
A
1
A
2
A
3
A
4
CS
I/O
1
I/O
2
I/O
3
1
2
3
4
5
6
7
8
9
44 A
15
43 A
14
42 A
13
41 OE
40 UB
39 LB
38 I/O
16
37 I/O
15
36 I/O
14
D
Vss
I/O4
N.C
A7
I/O12
Vcc
C
I/O2
I/O3
A5
A6
I/O11
I/O10
B
I/O1
UB
A3
A4
CS
I/O9
A
LB
OE
A0
A1
A2
N.C
I/O
4
10
Vcc 11
Vss 12
I/O
5
13
I/O
6
14
I/O
7
15
I/O
8
16
WE 17
A
5
18
A
6
19
A
7
20
A
8
21
N.C 22
SOJ/
TSOP2
35 I/O
13
34 Vss
33 Vcc
32 I/O
12
31 I/O
11
30 I/O
10
29 I/O
9
28 N.C
27 A
12
26 A
11
25 A
10
24 A
9
23 N.C
H
N.C
A8
A9
A10
A11
N.C
G
I/O8
N.C
A12
A13
WE
I/O16
F
I/O7
I/O6
A14
A15
I/O14
I/O15
E
Vcc
I/O5
N.C
N.C
I/O13
Vss
48-CSP
ABSOLUTE MAXIMUM RATINGS*
Parameter
Voltage on Any Pin Relative to V
SS
Voltage on V
CC
Supply Relative to V
SS
Power Dissipation
Storage Temperature
Operating Temperature
Commercial
Industrial
Symbol
V
IN
, V
OUT
V
CC
P
d
T
STG
T
A
T
A
Rating
-0.5 to V
CC
+0.5
-0.5 to 7.0
1
-65 to 150
0 to 70
-40 to 85
Unit
V
V
W
°C
°C
°C
*
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS*
(TA= to 70°C)
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.2
-0.5**
Typ
5.0
0
-
-
Max
5.5
0
V
CC
+0.5***
0.8
Unit
V
V
V
V
* The above parameters are also guaranteed at industrial temperature range.
**
V
IL
(Min) = -2.0V a.c(Pulse Width
≤
8ns) for I
≤
20mA.
***
V
IH
(Max) = V
CC +
2.0V a.c(Pulse Width
≤
8ns) for I
≤
20mA.
-3-
Revision 3.0
March 1999
KM6161002C/CL, KM6161002CI/CLI
CMOS SRAM
DC AND OPERATING CHARACTERISTICS*
(T
A
=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)
Parameter
Input Leakage Current
Output Leakage Current
Operating Current
Symbol
I
LI
I
LO
I
CC
Test Conditions
V
IN
=V
SS
to V
CC
CS=V
IH
or OE=V
IH
or WE=V
IL
V
OUT
=V
SS
to V
CC
Min. Cycle, 100% Duty
CS=V
IL,
V
IN
= V
IH
or V
IL,
I
OUT
=0mA
12ns
15ns
20ns
Standby Current
I
SB
I
SB1
Min. Cycle, CS=V
IH
f=0MHz, CS
≥V
CC
-0.2V,
V
IN
≥V
CC
-0.2V or V
IN
≤0.2V
I
OL
=8mA
I
OH
=-4mA
I
OH1
=-0.1mA
Normal
L-Ver.
Min
-2
-2
-
-
-
-
-
-
-
2.4
-
Max
2
2
95
93
90
30
5
0.5
0.4
-
3.95
V
V
V
mA
mA
Unit
µA
µA
mA
Output Low Voltage Level
Output High Voltage Level
V
OL
V
OH
V
OH1
**
* The above parameters are also guaranteed at industrial temperature range.
** V
CC
=5.0V±5%, Temp.=25°C
CAPACITANCE*
(T
A
=25°C, f=1.0MHz)
Item
Input/Output Capacitance
Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol
C
I/O
C
IN
Test Conditions
V
I/O
=0V
V
IN
=0V
MIN
-
-
Max
8
6
Unit
pF
pF
AC CHARACTERISTICS
(T
A
=0 to 70°C, V
CC
=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter
Input Pulse Levels
Input Rise and Fall Times
Input and Output timing Reference Levels
Output Loads
* The above test conditions are also applied at industrial temperature range.
Value
0V to 3V
3ns
1.5V
See below
Output Loads(A)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
R
L
= 50Ω
+5.0V
D
OUT
V
L
= 1.5V
Z
O
= 50Ω
30pF*
D
OUT
480Ω
255
Ω
5pF*
* Capacitive Load consists of all components of the
test environment.
* Including Scope and Jig Capacitance
-4-
Revision 3.0
March 1999
KM6161002C/CL, KM6161002CI/CLI
READ CYCLE*
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
UB, LB Access Time
Chip Enable to Low-Z Output
UB, LB Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
UB, LB Disable to High-Z Output
Output Hold from Address Change
Chip Selection to Power Up Time
Chip Selection to Power DownTime
Symbol
t
RC
t
AA
t
CO
t
OE
t
BA
t
LZ
t
BLZ
t
OLZ
t
HZ
t
OHZ
t
BHZ
t
OH
t
PU
t
PD
KM6161002C/CL-12
Min
12
-
-
-
-
3
0
0
0
0
0
3
0
-
Max
-
12
12
6
6
-
-
-
6
6
6
-
-
12
KM6161002C/CL-15
Min
15
-
-
-
-
3
0
0
-
-
-
3
0
-
Max
-
15
15
7
7
-
-
-
7
7
7
-
-
15
CMOS SRAM
KM6161002C/CL-20
Min
20
-
-
-
-
3
0
0
-
-
-
3
0
-
Max
-
20
20
9
9
-
-
-
9
9
9
-
-
20
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
WRITE CYCLE*
Parameter
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
Write Pulse Width(OE High)
Write Pulse Width(OE Low)
UB, LB Valid to End of Write
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Symbol
t
WC
t
CW
t
AS
t
AW
t
WP
t
WP1
t
BW
t
WR
t
WHZ
t
DW
t
DH
t
OW
KM6161002C/CL-12
Min
12
8
0
8
8
12
8
0
0
6
0
3
Max
-
-
-
-
-
-
-
-
6
-
-
-
KM6161002C/CL-15
Min
15
9
0
9
9
15
9
0
0
7
0
3
Max
-
-
-
-
-
-
-
-
7
-
-
-
KM6161002C/CL-20
Min
20
10
0
10
10
20
10
0
0
8
0
3
Max
-
-
-
-
-
-
-
-
9
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
* The above parameters are also guaranteed at industrial temperature range.
微控制器 MCU
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
