CAV25010, CAV25020,
CAV25040
EEPROM Serial 1/2/4-Kb SPI
Automotive Grade 1
Description
The CAV25010/20/40 are a EEPROM Serial 1/2/4−Kb SPI
Automotive Grade 1 devices internally organized as
128x8/256x8/512x8 bits. They feature a 16−byte page write buffer and
support the Serial Peripheral Interface (SPI) protocol. The device is
enabled through a Chip Select (CS) input. In addition, the required bus
signals are a clock input (SCK), data input (SI) and data output (SO)
lines. The HOLD input may be used to pause any serial
communication with the CAV25010/20/40 device. These devices
feature software and hardware write protection, including partial as
well as full array protection.
Features
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SOIC−8
V SUFFIX
CASE 751BD
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATION
CS
SO
WP
V
SS
SOIC (V), TSSOP (Y)
For the location of Pin 1, please consult the
corresponding package drawing.
1
V
CC
HOLD
SCK
SI
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Automotive Temperature Grade 1 (−40°C to +125°C)
10 MHz SPI Compatible
2.5 V to 5.5 V Supply Voltage Range
SPI Modes (0,0) & (1,1)
16−byte Page Write Buffer
Self−timed Write Cycle
Hardware and Software Protection
Block Write Protection
−
Protect 1/4, 1/2 or Entire EEPROM Array
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
SOIC and TSSOP 8−Lead Packages
These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
V
CC
PIN FUNCTION
Pin Name
CS
SO
WP
V
SS
SI
SCK
HOLD
V
CC
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
SI
CS
WP
HOLD
SCK
V
SS
CAV25010
CAV25020
CAV25040
SO
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Figure 1. Functional Symbol
©
Semiconductor Components Industries, LLC, 2012
June, 2018
−
Rev. 1
1
Publication Order Number:
CAV25010/D
CAV25010, CAV25020, CAV25040
MARKING DIAGRAMS
25010E = CAV25010
25020E = CAV25020
25040E = CAV25040
A
= Assembly Location
Y
= Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of
XXX =
Assembly Lot Number
G
= Pb−Free Package
S01E = CAV25010
S02E = CAV25020
S04E = CAV25040
A
= Assembly Location
Y
= Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
XXX = Last Three Digits of
XXX =
Assembly Lot Number
G
= Pb−Free Package
25xx0E
AYMXXX
G
SxxE
AYMXXX
G
(TSSOP−8)
(SOIC−8)
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Operating Temperature
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
Ratings
−45
to +130
−65
to +150
−0.5
to V
CC
+ 0.5
Units
°C
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
Table 3. D.C. OPERATING CHARACTERISTICS
(
V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.)
Symbol
I
CCR
I
CCW
I
SB1
I
SB2
I
L
I
LO
V
IL
V
IH
V
OL
V
OH
Parameter
Supply Current (Read Mode)
Supply Current (Write Mode)
Standby Current
Standby Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 3.0 mA
I
OH
=
−1.6
mA
V
CC
−
0.8 V
Test Conditions
Read, V
CC
= 5.5 V, 10 MHz, SO open
Write, V
CC
= 5.5 V, 10 MHz, SO open
V
IN
= GND or V
CC
, CS = V
CC
,
WP = V
CC
, V
CC
= 5.5 V
V
IN
= GND or V
CC
, CS = V
CC
,
WP = GND, V
CC
= 5.5 V
V
IN
= GND or V
CC
CS = V
CC
,
V
OUT
= GND or V
CC
−2
−1
−0.5
0.7 V
CC
Min
Max
2
2
2
5
2
2
0.3 V
CC
V
CC
+ 0.5
0.4
Units
mA
mA
mA
mA
mA
mA
V
V
V
V
Table 4. PIN CAPACITANCE
(Note 2) (T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0 V)
Symbol
C
OUT
C
IN
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
Test
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Min
Typ
Max
8
8
Units
pF
pF
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C.
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CAV25010, CAV25020, CAV25040
Table 5. A.C. CHARACTERISTICS
(T
A
=
−40°C
to +125°C) (Note 4)
V
CC
= 2.5 V
−
5.5 V
Symbol
f
SCK
t
SU
t
H
t
WH
t
WL
t
LZ
t
RI
(Note 5)
t
FI
(Note 5)
t
HD
t
CD
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
CNS
t
CNH
t
WPS
t
WPH
t
WC
(Note 6)
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
CS Setup Time
CS Hold Time
CS Inactive Setup Time
CS Inactive Hold Time
WP Setup Time
WP Hold Time
Write Cycle Time
40
30
30
20
20
10
10
5
0
20
25
0
10
35
Parameter
Min
DC
10
10
40
40
25
2
2
Max
10
Units
MHz
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
4. AC Test Conditions:
Input Pulse Voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times:
≤
10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
OL max
/I
OH max
; C
L
= 30 pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
6. t
WC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
Table 6. POWER−UP TIMING
(Notes 7, 8)
Symbol
t
PUR
t
PUW
Power−up to Read Operation
Power−up to Write Operation
Parameter
Min
0.1
0.1
Max
1
1
Units
ms
ms
7. This parameter is tested initially and after a design or process change that affects the parameter.
8. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable at the operating voltage until the specified operation can be initiated.
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CAV25010, CAV25020, CAV25040
Pin Description
Functional Description
SI:
The serial data input pin accepts op−codes, addresses
and data. In SPI modes (0,0) and (1,1) input data is latched
on the rising edge of the SCK clock input.
SO:
The serial data output pin is used to transfer data out of
the device. In SPI modes (0,0) and (1,1) data is shifted out
on the falling edge of the SCK clock.
SCK:
The serial clock input pin accepts the clock provided
by the host and used for synchronizing communication
between host and CAV25010/20/40.
CS:
The chip select input pin is used to enable/disable the
CAV25010/20/40. When CS is high, the SO output is
tri−stated (high impedance) and the device is in Standby
Mode (unless an internal write operation is in progress).
Every communication session between host and
CAV25010/20/40 must be preceded by a high to low
transition and concluded with a low to high transition of the
CS input.
WP:
The write protect input pin will allow all write
operations to the device when held high. When WP pin is
tied low all write operations are inhibited.
HOLD:
The HOLD input pin is used to pause transmission
between host and CAV25010/20/40, without having to
retransmit the entire sequence at a later time. To pause,
HOLD must be taken low and to resume it must be taken
back high, with the SCK input low during both transitions.
When not used for pausing, the HOLD input should be tied
to V
CC
, either directly or through a resistor.
CS
t
CNH
SCK
t
SU
SI
t
H
VALID
IN
t
V
t
HO
SO
HI−Z
VALID
OUT
t
RI
t
FI
t
CSS
t
WH
t
WL
The CAV25010/20/40 devices support the Serial
Peripheral Interface (SPI) bus protocol, modes (0,0) and
(1,1). The device contains an 8−bit instruction register. The
instruction set and associated op−codes are listed in Table 7.
Reading data stored in the CAV25010/20/40 is
accomplished by simply providing the READ command and
an address. Writing to the CAV25010/20/40, in addition to
a WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits in
a Status Register, as will be explained later.
After a high to low transition on the CS input pin, the
CAV25010/20/40 will accept any one of the six instruction
op−codes listed in Table 7 and will ignore all other possible
8−bit combinations. The communication protocol follows
the timing from Figure 2.
Table 7. INSTRUCTION SET
(Note 9)
Instruction
WREN
WRDI
RDSR
WRSR
READ
WRITE
Opcode
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
0000 X010
Operation
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
9. X = 0 for CAV25010, CAV25020. X = A8 for CAV25040
t
CS
t
CSH
t
CNS
t
V
t
DIS
HI−Z
Figure 2. Synchronous Data Timing
Status Register
The Status Register, as shown in Table 8, contains a
number of status and control bits.
The RDY (Ready) bit indicates whether the device is busy
with a write operation. This bit is automatically set to 1 during
an internal write cycle, and reset to 0 when the device is ready
to accept commands. For the host, this bit is read only.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
The BP0 and BP1 (Block Protect) bits determine which
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 9. The protected
blocks then become read−only.
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CAV25010, CAV25020, CAV25040
Table 8. STATUS REGISTER
7
1
6
1
5
1
4
1
3
BP1
2
BP0
1
WEL
0
RDY
Table 9. BLOCK PROTECTION BITS
Status Register Bits
BP1
0
0
1
1
BP0
0
1
0
1
None
CAV25010: 060−07F, CAV25020: 0C0−0FF, CAV25040: 180−1FF
CAV25010: 040−07F, CAV25020: 080−0FF, CAV25040: 100−1FF
CAV25010: 000−07F, CAV25020: 000−0FF, CAV25040: 000−1FF
Array Address Protected
Protection
No Protection
Quarter Array Protection
Half Array Protection
Full Array Protection
WRITE OPERATIONS
instruction to the CAV25010/20/40. Care must be taken to
The CAV25010/20/40 device powers up into a write
take the CS input high after the WREN instruction, as
disable state. The device contains a Write Enable Latch
(WEL) which must be set before attempting to write to the
otherwise the Write Enable Latch will not be properly set.
memory array or to the status register. In addition, the
WREN timing is illustrated in Figure 3. The WREN
address of the memory location(s) to be written must be
instruction must be sent prior to any WRITE or WRSR
outside the protected area, as defined by BP0 and BP1 bits
instruction.
from the status register.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 4. Disabling write
Write Enable and Write Disable
operations by resetting the WEL bit, will protect the device
The internal Write Enable Latch and the corresponding
against inadvertent writes.
Status Register WEL bit are set by sending the WREN
CS
SCK
SI
0
0
0
0
0
1
1
0
SO
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
Figure 3. WREN Timing
CS
SCK
SI
0
0
0
0
0
1
0
0
SO
HIGH IMPEDANCE
Dashed Line = mode (1, 1)
Figure 4. WRDI Timing
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