March 2008
HY[B/I]18T512400B2[C/F](L)
HY[B/I]18T512800B2[C/F](L)
HY[B/I]18T512160B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
Internet Data Sheet
Rev. 1.40
Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
Revision History: Rev. 1.40, 2008-03
Adapted internet edition
Corrected temperature range
Previous Revision: Rev. 1.30, 2008-02
Corrected all figures relating to DQS/DQS# in chapter 7 and chapter 8
Added more producs
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc@qimonda.com
qag_techdoc_A4, 4.20, 2008-01-25
10062006-YPTZ-CDR7
2
Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its main
characteristics.
1.1
Features
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• Off-Chip-Driver impedance adjustment (OCD) and
• 1.8 V
±
0.1 V Power Supply
1.8 V
±
0.1 V (SSTL_18) compatible I/O
On-Die-Termination (ODT) for better signal quality
• DRAM organizations with 4,8,16 data in/outputs
• Auto-Precharge operation for read and write bursts
• Double Data Rate architecture:
• Auto-Refresh, Self-Refresh and power saving Power-
– two data transfers per clock cycle
Down modes
– four internal banks for concurrent operation
• Operating temperature range 0 °C to 95 °C
• Programmable CAS Latency: 3, 4, 5 and 6
• Industrial temperature range -40 °C to 95 °C
• Programmable Burst Length: 4 and 8
• Average Refresh Period 7.8
μs
at a
T
CASE
lower
• Differential clock inputs (CK and CK)
than 85 °C, 3.9
μs
between 85 °C and 95 °C
• Bi-directional, differential data strobes (DQS and DQS) are
• Programmable self refresh rate via EMRS2 setting
transmitted / received with data. Edge aligned with read
• Programmable partial array refresh via EMRS2 settings
data and center-aligned with write data.
• DCC enabling via EMRS2 setting
• DLL aligns DQ and DQS transitions with clock
• Full and reduced Strength Data-Output Drivers
• 1KB page size for ×4 and ×8, 2KB page size for ×16
• DQS can be disabled for single-ended data strobe
operation
• Packages: PG-TFBGA-60, PG-TFBGA-84, P-TFBGA-60,
• Commands entered on each positive clock edge, data and
P-TFBGA-84
data mask are referenced to both edges of DQS
• All Speed grades faster than DDR2–400 comply with
• Data masks (DM) for write data
DDR2–400 timing specifications when run at a clock rate
• Posted CAS by programmable additive latency for better
of 200 MHz.
command and data bus efficiency
Rev. 1.40, 2008-03
10062006-YPTZ-CDR7
3
Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
CAS-RCD-RP latencies
Max. Clock Frequency
CL3
CL4
CL5
CL6
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Active Time
Min. Row Cycle Time
Min. Row Cycle Time
Precharge-All (4 banks)
command period
DDR2
–25F
–800D
5–5–5
–2.5
–800E
6–6–6
200
266
333
400
15
15
45
40
60
55
15
–3
–667C
4–4–4
200
333
333
–
12
12
45
40
57
52
12
–3S
–667D
5–5–5
200
266
333
–
15
15
45
40
60
55
15
–3.7
–533C
4–4–4
200
266
266
–
15
15
45
40
60
55
15
–5
–400B
3–3–3
200
200
–
–
15
15
40
40
55
55
15
Unit
Note
t
CK
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
1)
2)
1)
2)
f
CK3
f
CK4
f
CK5
f
CK6
t
RCD
t
RP
t
RAS
t
RAS
t
RC
t
RC
t
PREA
200
266
400
–
12.5
12.5
45
40
57.5
52.5
12.5
1) For products released before 01-09-2007.
2) Products released after 01-09-2007 can support
t
RAS.MIN
= 40 ns for all DDR2 speed sort.
1.2
Description
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 16 bit address bus for ×4 and ×8 organised components is
used to convey row, column and bank address information in
a RAS-CAS multiplexing style.
A 15 bit address bus for ×16 components is used to convey
row, column and bank address information in a RAS-CAS
multiplexing style.
The DDR2 device operates with a 1.8 V
±
0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is provided
along with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in TFBGA package.
The 512-Mbit DDR2 DRAM is a high-speed Double-Data-
Rate-Two CMOS Synchronous DRAM device containing 536,
870, 912 bits and internally configured as a quad-bank
DRAM. The 512-Mbit device is organized as 32 Mbit
×4
I/O
×4
banks or 16 Mbit
×8
I/O
×4
banks or 8 Mbit
×16
I/O
×4
banks
chip.
These synchronous devices achieve high speed transfer
rates starting at 400 Mb/sec/pin for general applications. See
Table 1
for performance figures.
The device is designed to comply with all DDR2 DRAM key
features:
1. Posted CAS with additive latency.
2. Write latency = read latency - 1.
3. Normal and weak strength data-output driver.
4. Off-Chip Driver (OCD) impedance adjustment.
5. On-Die Termination (ODT) function.
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
Rev. 1.40, 2008-03
10062006-YPTZ-CDR7
4
Internet Data Sheet
HY[B/I]18T512[40/80/16]0B2[C/F](L)
512-Mbit Double-Data-Rate-Two SDRAM
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type
1)
Org.
Speed
CAS-RCD-RP
Latencies
2)3)4)
Clock (MHz)
Package
Note
5)
Standard Temperature Range (0 °C - +95 °C)
DDR2-800E( 6-6-6 )
HYB18T512400B2FL-2.5
HYB18T512800B2FL-2.5
HYB18T512160B2FL-2.5
HYB18T512800B2F-2.5
HYB18T512400B2F-2.5
HYB18T512160B2F-2.5
DDR2-800D( 5-5-5 )
HYB18T512400B2FL-25F
HYB18T512800B2FL-25F
HYB18T512160B2FL-25F
HYB18T512800B2F-25F
HYB18T512400B2F-25F
HYB18T512160B2F-25F
DDR2-667D( 5-5-5 )
HYB18T512400B2FL-3S
HYB18T512800B2FL-3S
HYB18T512160B2FL-3S
HYB18T512800B2F-3S
HYB18T512400B2F-3S
HYB18T512160B2F-3S
DDR2-533C( 4-4-4 )
HYB18T512400B2FL-3.7
HYB18T512800B2FL-3.7
HYB18T512160B2FL-3.7
HYB18T512800B2F-3.7
HYB18T512400B2F-3.7
HYB18T512160B2F-3.7
DDR2-400B( 3-3-3 )
HYB18T512160B2FL-5
×16
DDR2-400B
3-3-3
200
PG-TFBGA-84
×4
×8
×16
×8
×4
×16
DDR2-533C
DDR2-533C
DDR2-533C
DDR2-533C
DDR2-533C
DDR2-533C
4-4-4
4-4-4
4-4-4
4-4-4
4-4-4
4-4-4
266
266
266
266
266
266
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
×4
×8
×16
×8
×4
×16
DDR2-667D
DDR2-667D
DDR2-667D
DDR2-667D
DDR2-667D
DDR2-667D
5-5-5
5-5-5
5-5-5
5-5-5
5-5-5
5-5-5
333
333
333
333
333
333
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
×4
×8
×16
×8
×4
×16
DDR2-800D
DDR2-800D
DDR2-800D
DDR2-800D
DDR2-800D
DDR2-800D
5-5-5
5-5-5
5-5-5
5-5-5
5-5-5
5-5-5
400
400
400
400
400
400
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
×4
×8
×16
×8
×4
×16
DDR2-800E
DDR2-800E
DDR2-800E
DDR2-800E
DDR2-800E
DDR2-800E
6-6-6
6-6-6
6-6-6
6-6-6
6-6-6
6-6-6
400
400
400
400
400
400
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
PG-TFBGA-60
PG-TFBGA-60
PG-TFBGA-84
Rev. 1.40, 2008-03
10062006-YPTZ-CDR7
5
FPGA/CPLD
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
