NB3M8302C
3.3 V 200 MHz 1:2
LVCMOS/LVTTL Low Skew
Fanout Buffer
Description
The NB3M8302C is 1:2 fanout buffer with LVCMOS/LVTTL input
and output. The device supports the core supply voltage of 3.3 V (V
DD
pin) and output supply voltage of 2.5 V or 3.3 V (V
DDO
pin). The
V
DDO
pin powers the two single ended LVCMOS/LVTTL outputs.
The NB3M8302C is Form, Fit and Function (pin to pin) compatible
to ICS8302 and ICS8302I. The NB3M8302C is qualified for industrial
operating temperature range.
Features
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MARKING
DIAGRAMS*
8
1
SOIC−8
D SUFFIX
CASE 751
A
L
Y
W
G
8
8302C
ALYWG
G
1
•
•
•
•
•
•
Input Clock Frequency up to 200 MHz
Low Output to Output Skew: 25 ps typical
Low Part to Part Skew: 250 ps typical
Low Additive RMS Phase Jitter
Input Clock Accepts LVCMOS/ LVTTL Levels
Operating Voltage:
♦
Core Supply: V
DD
= 3.3 V
±5%
♦
Output Supply: V
DDO
= 3.3 V
±5%
or 2.5 V
±5%
•
Operating Temperature Range:
♦
Industrial: −40°C to +85°C
•
These Devices are Pb−Free and are RoHS Compliant
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
Figure 1. Block Diagram
©
Semiconductor Components Industries, LLC, 2014
1
December, 2014 − Rev. 3
Publication Order Number:
NB3M8302C/D
NB3M8302C
Figure 2. Pin Configuration
(Top View)
Table 1. PIN DESCRIPTION
Pin Number
1, 6
2
3
4, 7
5
8
Name
VDDO
VDD
CLK
GND
Q1
Q0
Type
Output Power
Input and Core Power
LVCMOS/LVTTL Input
Ground
LVCMOS/LVTTL Output
LVCMOS/LVTTL Output
Clock output Supply pin.
Input and Core Supply pin.
Clock Input. Internally pull−down.
Supply Ground.
LVCMOS/LVTTL Clock output.
LVCMOS/LVTTL Clock output.
Description
Table 2. MAXIMUM RATINGS
Symbol
V
DD,
V
DDO
V
I
T
stg
q
JA
Power Supply
Input Voltage
Storage Temperature
Thermal Resistance (Junction to Ambient)
SOIC−8
Thermal Resistance (Junction to Case)
(Note 1)
Wave Solder
Moisture Sensitivity
SOIC−8
3 sec
Indefinite Time Out of Drypack
(Note 2)
Level 1
0 lfpm
500 lfpm
Parameter
Condition
Min
−
−0.5
−65
Max
4.6
VDD + 0.5 V
+150
80
55
12−17
265
_C/W
_C
Unit
V
V
_C
_C/W
q
JC
T
sol
MSL
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board – 2S2P (2 signal, 2 power)
2. For additional information, see Application Note AND8003/D.
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2
NB3M8302C
Table 3. DC OPERATING CHARACTERISTICS
(V
DD
= V
DDO
= 3.3 V±5%, V
DD
= 3.3 V±5%, V
DDO
= 2.5 V±5%; T
A
= −40°C to +85°C)
Symbol
R
IN
C
IN
R
OUT
C
PD
Parameter
Input Pull−down Resistor (CLK Pin)
Input Capacitance
Output Impedance (Note 3)
Power Dissipation Capacitance (per output)
V
DD
= V
DDO
= 3.465 V
V
DD
= 3.465 V, V
DDO
= 2.625 V
V
DD
I
IH
I
IL
Core Supply Voltage
Input High Current
Input Low Current
V
IN
= V
DD
= 3.465 V
V
DD
3.465 V, V
IN
= 0.0 V
−0.5
3.135
5
Condition
Min
Typ
51
4
7
22
16
3.3
3.465
150
V
mA
mA
12
Max
Unit
kW
pF
W
pF
3. Outputs terminated with 50
W
to V
DDO
/2. See Figure 4 for supply considerations.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. DC OPERATING CHARACTERISTICS
(T
A
= −40°C to +85°C)
Symbol
Parameter
Condition
Min
Max
Unit
V
DD
= 3.3 V+5%, V
DDO
= 2.5 V+5%
V
DDO
V
OH
Output Supply Voltage
Output HIGH Voltage
I
OH
= −16 mA
I
OH
= −100
mA
50
W
to V
DDO
/2
V
OL
Output LOW Voltage
I
OL
= 16 mA
I
OL
= 100
mA
50
W
to V
DDO
/2
V
DD
= V
DDO
= 3.3 V+5%
V
DDO
V
OH
Output Supply Voltage
Output HIGH Voltage
I
OH
= −16 mA
I
OH
= −100
mA
50
W
to V
DDO
/2
V
OL
Output LOW Voltage
I
OL
= 16 mA
I
OL
= 100
mA
50
W
to V
DDO
/2
3.135
2.9
2.9
2.6
0.15
0.2
0.5
V
3.465
V
V
2.375
2.1
2.2
1.8
0.15
0.2
0.5
V
2.625
V
V
Table 5. DC OPERATING CHARACTERISTICS
(T
A
= −40°C to +85°C; V
DD
= V
DDO
= 3.3 V±5%, V
DD
= 3.3 V±5%, V
DDO
= 2.5
V±5%)
Symbol
I
DD
I
DDO
V
IH
V
IL
Parameter
Quiescent Power Supply Current
Quiescent Power Supply Current
Input HIGH Voltage
Input LOW Voltage
Condition
No Load
No Load
2
−0.3
Min
Max
13
4
V
DD
+ 0.3
1.3
Unit
mA
mA
V
V
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3
NB3M8302C
Table 6. AC CHARACTERISTICS
(Note 4)
Symbol
Parameter
Condition
Min
Typ
Max
Unit
T
A
= −405C to +855C; V
DD
= V
DDO
= 3.3 V+5%
F
IN
t
PLH
t
SKEW
Input Frequency
Propagation Delay (Note 5)
Output to Output Skew(Note 6)
Part to Part Skew (Note 6)
t
SKEWDC
Output Duty Cycle (see Figure 3)
Fin
v
133 MHz
133 MHz
<
Fin
<
200 MHz
tr/tf
Output rise and fall times (Note 7)
20% to 80%, RS = 33
W
45
40
250
Fin = 200 MHz
1.9
25
250
200
3.1
85
800
55
60
800
ps
%
MHz
ns
ps
T
A
= −405C to +855C; V
DD
= 3.3 V+5%, V
DDO
= 2.5 V+5%
F
IN
t
PLH
t
SKEW
Input Frequency
Propagation Delay (Note 5)
Output to Output Skew(Note 6)
Part to Part Skew (Note 6)
t
SKEWDC
Output Duty Cycle (see Figure 3)
Fin
v
133 MHz
133 MHz
<
Fin
<
200 MHz
tr/tf
Output rise and fall times (Note 7)
20% to 80%, RS = 33
W
45
40
200
Fin = 200 MHz
2.0
25
250
200
3.3
85
800
55
60
650
ps
%
MHz
ns
ps
4. Clock input with 50% duty cycle. Outputs terminated with 50
W
to V
DDO
/2. See Figures 3 and 4.
5. Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
6. Similar input conditions and the same supply voltages. Measured at V
DDO
/2. See Figures 3 and 4.
7. RS is Series Resistance at the clock outputs.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
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NB3M8302C
Figure 3. AC Reference Measurement
V
DD
V
DDO
Z
O
= 50
W
NB3M8302C
Qx
50
W
D
Receiver /
Scope
DUT
GND
Spec Condition:
V
DD
= V
DDO
= 3.3 V
±5%
V
DD
= 3.3 V
±5%;
V
DDO
= 2.5 V
±5%
TEST SETUP V
DD
:
1.65 V
±5%
2.05 V
±5%
TEST SETUP V
DDO
:
1.65 V
±5%
1.25 V
±5%
TEST SETUP DUT GND:
−1.65 V
±5%
−1.25 V
±5%
Figure 4. Output Driver Typical Device Evaluation and Termination Setup
ORDERING INFORMATION
Device
NB3M8302CDG
NB3M8302CDR2G
Package
SOIC−8
(Pb−Free)
SOIC−8
(Pb−Free)
Shipping
†
98 Units / Rail
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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