MTB9N25E
Designer’s™ Data Sheet
TMOS E−FET.™
High Energy Power FET
D
2
PAK for Surface Mount
D
2
PAK
N−Channel Enhancement−Mode Silicon
Gate
The
package has the capability of housing a larger die than
any existing surface mount package which allows it to be used in
applications that require the use of surface mount components with
higher power and lower R
DS(on)
capabilities. This advanced TMOS
E−FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
drain−to−source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
•
Robust High Voltage Termination
•
Avalanche Energy Specified
•
Source−to−Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
•
Diode is Characterized for Use in Bridge Circuits
•
I
DSS
and V
DS(on)
Specified at Elevated Temperature
•
Short Heatsink Tab Manufactured — Not Sheared
•
Specially Designed Leadframe for Maximum Power Dissipation
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TMOS POWER FET
9.0 AMPERES, 250 VOLTS
R
DS(on)
= 0.45
W
D
2
PAK
CASE 418B−02
Style 2
D
®
G
S
©
Semiconductor Components Industries, LLC, 2006
August, 2006
−
Rev. 1
1
Publication Order Number:
MTB9N25E/D
MTB9N25E
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Drain−to−Gate Voltage (R
GS
= 1.0 MΩ)
Gate−to−Source Voltage — Continuous
— Non−Repetitive (t
p
≤
10 ms)
Drain Current — Continuous
— Continuous @ 100°C
— Single Pulse (t
p
≤
10
μs)
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ T
A
= 25°C
(1)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche Energy — Starting T
J
= 25°C
(V
DD
= 80 Vdc, V
GS
= 10 Vdc, Peak I
L
= 9.0 Apk, L = 3.0 mH, R
G
= 25
Ω)
Thermal Resistance
— Junction to Case
— Junction to Ambient
— Junction to Ambient
(1)
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
Value
250
250
±
20
±
40
9.0
5.7
32
80
0.64
2.5
−
55 to 150
122
1.56
62.5
50
260
°C/W
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
Watts
W/°C
Watts
°C
mJ
I
DM
P
D
T
J
, T
stg
E
AS
R
θJC
R
θJA
R
θJA
T
L
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
°C
Designer’s Data for “Worst Case” Conditions
— The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E−FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred
devices are Motorola recommended choices for future use and best overall value.
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MTB9N25E
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
μAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 250 Vdc, V
GS
= 0 Vdc)
(V
DS
= 250 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
μAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance (V
GS
= 10 Vdc, I
D
= 4.5 Adc)
Drain−to−Source On−Voltage
(V
GS
= 10 Vdc, I
D
= 9.0 Adc)
(V
GS
= 10 Vdc, I
D
= 4.5 Adc, T
J
= 125°C)
Forward Transconductance (V
DS
= 15 Vdc, I
D
= 4.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(V
DD
= 125 Vdc, I
D
= 9.0 Adc,
V
GS
= 10 Vdc,
R
G
= 9.1
Ω)
t
d(on)
t
r
t
d(off)
t
f
Q
T
(V
DS
= 200 Vdc, I
D
= 9.0 Adc,
V
GS
= 10 Vdc)
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (1)
(I
S
= 9.0 Adc, V
GS
= 0 Vdc )
(I
S
= 9.0 Adc, V
GS
= 0 Vdc , T
J
= 125°C)
V
SD
Vdc
—
—
—
—
—
—
0.9
0.81
191
126
65
1.387
1.5
—
—
—
—
—
μC
nH
—
—
4.5
7.5
—
nH
—
ns
—
—
—
—
—
—
—
—
10
36
27
26
26
4.8
12.7
9.2
20
70
55
50
40
—
—
—
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
—
—
—
783
144
32
1100
200
65
pF
V
GS(th)
2.0
—
—
—
—
3.0
3.0
7.0
0.37
3.5
—
5.2
4.0
—
0.45
5.4
4.7
—
mhos
Vdc
mV/°C
Ohm
Vdc
V
(BR)DSS
Vdc
250
—
—
—
—
—
328
—
—
—
—
—
10
100
100
mV/°C
μAdc
Symbol
Min
Typ
Max
Unit
I
DSS
I
GSS
nAdc
R
DS(on)
V
DS(on)
g
FS
Reverse Recovery Time
(See Figure 14)
t
rr
(I
S
= 9.0 Adc, V
GS
= 0 Vdc,
dl
S
/dt = 100 A/μs)
t
a
t
b
Q
RR
L
D
L
S
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
(1) Pulse Test: Pulse Width
≤
300
μs,
Duty Cycle
≤
2%.
(2) Switching characteristics are independent of operating junction temperature.
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MTB9N25E
TYPICAL ELECTRICAL CHARACTERISTICS
18
I D , DRAIN CURRENT (AMPS)
15
12
9
6V
6
3
0
5V
T
J
= 25°C
V
GS
= 10 V
9V
18
8V
I D , DRAIN CURRENT (AMPS)
7V
15
12
9
6
3
0
25°C
100°C
V
DS
≥
10 V
T
J
= −55°C
0
2
4
6
8
10
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
12
2
3
4
5
6
7
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)
1.2
V
GS
= 10 V
1.0
0.8
T
J
= 100°C
0.6
0.4
0.2
0
25°C
0.6
Figure 2. Transfer Characteristics
T
J
= 25°C
0.5
V
GS
= 10 V
0.4
15 V
− 55°C
0
3
6
9
12
I
D
, DRAIN CURRENT (AMPS)
15
18
0.3
0
3
6
9
12
I
D
, DRAIN CURRENT (AMPS)
15
Figure 3. On−Resistance versus Drain Current
and Temperature
2.5
V
GS
= 10 V
I
D
= 4.5 A
2.0
I DSS , LEAKAGE (nA)
1.5
100
1000
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
RDS(on) , DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
V
GS
= 0 V
T
J
= 125°C
100°C
10
25°C
1
1.0
0.5
0
−50
−25
0
25
50
75
100
T
J
, JUNCTION TEMPERATURE (°C)
125
150
0.1
0
50
100
150
200
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
2
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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MTB9N25E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Δt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate
of average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
2000
1600
C, CAPACITANCE (pF)
C
iss
V
DS
= 0 V
V
GS
= 0 V
T
J
= 25°C
The capacitance (C
iss
) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to
the on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves
would maintain a value of unity regardless of the switching
speed. The circuit used to obtain the data is constructed to
minimize common inductance in the drain and gate circuit
loops and is believed readily achievable with board
mounted components. Most power electronic loads are
inductive; the data in the figure is taken with a resistive load,
which approximates an optimally snubbed inductive load.
Power MOSFETs may be safely operated into an inductive
load; however, snubbing reduces switching losses.
1200
C
rss
C
iss
800
400
0
C
rss
10
5
V
GS
0
V
DS
5
C
oss
10
15
20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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