simultaneous sampling 14-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
They are perfect for demanding communications applica-
tions with AC performance that includes 73.1dB SNR and
88dB spurious free dynamic range (SFDR). Ultralow jitter
of 0.15ps
RMS
allows undersampling of IF frequencies with
excellent noise performance.
DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 1.2LSB
RMS
.
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode). The LVDS drivers have
optional internal termination and adjustable output levels
to ensure clean signal integrity.
The ENC
+
and ENC
–
inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
n
n
n
n
n
n
n
n
4-Channel Simultaneous Sampling ADC
73.1dB SNR
88dB SFDR
Low Power: 558mW/450mW/376mW Total,
140mW/113mW/94mW per Channel
Single 1.8V Supply
Serial LVDS Outputs: 1 or 2 Bits per Channel
Selectable Input Ranges: 1V
P-P
to 2V
P-P
800MHz Full Power Bandwidth S/H
Shutdown and Nap Modes
Serial SPI Port for Configuration
Pin Compatible 14-Bit and 12-Bit Versions
52-Pin (7mm × 8mm) QFN Package
applicaTions
n
n
n
n
n
n
Communications
Cellular Base Stations
Software Defined Radios
Portable Medical Imaging
Multichannel Data Acquisition
Nondestructive Testing
L,
LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V
V
DD
CHANNEL 1
ANALOG
INPUT
CHANNEL 2
ANALOG
INPUT
CHANNEL 3
ANALOG
INPUT
CHANNEL 4
ANALOG
INPUT
ENCODE
INPUT
S/H
14-BIT
ADC CORE
14-BIT
ADC CORE
14-BIT
ADC CORE
14-BIT
ADC CORE
DATA
SERIALIZER
1.8V
OV
DD
OUT1A
OUT1B
OUT2A
OUT2B
OUT3A
OUT3B
OUT4A
OUT4B
DATA
CLOCK
OUT
FRAME
GND
OGND
217514 TA01
LTC2175-14, 125Msps,
2-Tone FFT, f
IN
= 70MHz and 75MHz
0
–10
–20
AMPLITUDE (dBFS)
–30
–40
–50
–60
–70
–80
S/H
S/H
SERIALIZED
LVDS
OUTPUTS
S/H
–90
–100
–110
–120
PLL
0
10
20
30
40
FREQUENCY (MHz)
50
60
217514 TA01b
21754314fa
1
LTC2175-14/
LTC2174-14/LTC2173-14
absoluTe MaxiMuM raTings
(Notes 1, 2)
pin conFiguraTions
TOP VIEW
PAR/SER
OUT1A
+
OUT1A
–
OUT1B
+
OUT4A
–
OUT1B
–
40 OUT2A
+
39 OUT2A
–
38 OUT2B
+
37 OUT2B
–
36 DCO
+
35 DCO
–
53
GND
34 OV
DD
33 OGND
32 FR
+
31 FR
–
30 OUT3A
+
29 OUT3A
–
28 OUT3B
+
27 OUT3B
–
15 16 17 18 19 20 21 22 23 24 25 26
V
DD
V
DD
ENC
+
–
–
Supply Voltages
V
DD
, OV
DD
................................................ –0.3V to 2V
Analog Input Voltage (A
IN+
, A
IN –
,
PAR/SER, SENSE) (Note 3) .......... –0.3V to (V
DD
+ 0.2V)
Digital Input Voltage (ENC
+
, ENC
–
,
CS,
SDI, SCK) (Note 4) .................................... –0.3V to 3.9V
SDO (Note 4)............................................. –0.3V to 3.9V
Digital Output Voltage ................ –0.3V to (OV
DD
+ 0.3V)
Operating Temperature Range
LTC2175C, 2174C, 2173C ......................... 0°C to 70°C
LTC2175I, 2174I, 2173I ........................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
SENSE
V
REF
GND
52 51 50 49 48 47 46 45 44 43 42 41
A
IN1+
1
A
IN1–
2
V
CM12
3
A
IN2+
4
A
IN2–
5
REFH 6
REFH 7
REFL 8
REFL 9
A
IN3+
10
A
IN3–
11
V
CM34
12
A
IN4+
13
A
IN4–
14
OUT4B
+
OUT4A
+
CS
SCK
SDI
GND
ENC
GND
SDO
V
DD
V
DD
UKG PACKAGE
52-LEAD (7mm
×
8mm) PLASTIC QFN
T
JMAX
= 150°C,
θ
JA
= 28°C/W
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC2175CUKG-14#PBF
LTC2175IUKG-14#PBF
LTC2174CUKG-14#PBF
LTC2174IUKG-14#PBF
LTC2173CUKG-14#PBF
LTC2173IUKG-14#PBF
TAPE AND REEL
LTC2175CUKG-14#TRPBF
LTC2175IUKG-14#TRPBF
LTC2174CUKG-14#TRPBF
LTC2174IUKG-14#TRPBF
LTC2173CUKG-14#TRPBF
LTC2173IUKG-14#TRPBF
PART MARKING*
LTC2175UKG-14
LTC2175UKG-14
LTC2174UKG-14
LTC2174UKG-14
LTC2173UKG-14
LTC2173UKG-14
PACKAGE DESCRIPTION
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
TEMPERATURE RANGE
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to:
http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to:
http://www.linear.com/tapeandreel/
OUT4B
21754314fa
2
LTC2175-14/
LTC2174-14/LTC2173-14
converTer characTerisTics
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
l
LTC2175-14
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Gain Error
Offset Drift
Full-Scale Drift
Gain Matching
Offset Matching
Transition Noise
External Reference
Internal Reference
External Reference
External Reference
Differential Analog Input
(Note 7)
Internal Reference
External Reference
MIN
14
–4.1
–0.9
–12
–2.6
±1.2
±0.3
±3
–1.3
–1.3
±20
±35
±25
±0.2
±3
1.2
4.1
0.9
12
0
TYP
MAX
MIN
14
LTC2174-14
TYP
±1
±0.3
±3
–1.3
–1.3
±20
±35
±25
±0.2
±3
1.2
MAX
3.25
0.8
12
0
14
LTC2173-14
MIN
–2.75
–0.8
–12
–2.6
TYP
±1
±0.3
±3
–1.3
–1.3
±20
±35
±25
±0.2
±3
1.2
MAX
2.75
0.8
12
0
UNITS
Bits
LSB
LSB
mV
%FS
%FS
µV/°C
ppm/°C
ppm/°C
%FS
mV
LSB
RMS
Differential Analog Input (Note 6)
l
l
l
l
–3.25
–0.8
–12
–2.6
analog inpuT
SYMBOL PARAMETER
V
IN
V
IN(CM)
V
SENSE
I
INCM
I
IN1
I
IN2
I
IN3
t
AP
t
JITTER
CMRR
BW-3B
The
l
denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
1.7V < V
DD
< 1.9V
Differential Analog Input (Note 8)
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
0 < A
IN+
, A
IN–
< V
DD
,
0 < PAR/SER < V
DD
0.625 < SENSE < 1.3V
l
l
l
l
l
l
MIN
V
CM
– 100mV
0.625
TYP
1 to 2
V
CM
1.250
155
130
100
MAX
V
CM
+ 100mV
1.300
UNITS
V
P-P
V
V
µA
µA
µA
Analog Input Range (A
IN+
– A
IN–
)
Analog Input Common Mode (A
IN+
+ A
IN–
)/2
Analog Input Common Mode Current
External Voltage Reference Applied to SENSE External Reference Mode
Analog Input Leakage Current No Encode
PAR/SER Input Leakage Current
SENSE Input Leakage Current
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
–1
–3
–6
0
0.15
80
1
3
6
µA
µA
µA
ns
ps
RMS
dB
MHz
Figure 6 Test Circuit
800
21754314fa
3
LTC2175-14/
LTC2174-14/LTC2173-14
The
l
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
LTC2175-14
SYMBOL
SNR
PARAMETER
Signal-to-Noise Ratio
CONDITIONS
5MHz Input
70MHz Input
140MHz Input
l
DynaMic accuracy
LTC2174-14
MIN
70.7
TYP
73
72.9
72.6
88
85
82
90
90
90
73
72.6
72
–90
–105
MAX
LTC2173-14
MIN
70.9
TYP
73
72.9
72.5
88
85
82
90
90
90
72.9
72.6
72
–90
–105
MAX
UNITS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
dBc
MIN
71.1
TYP
73.1
73
72.6
88
85
82
90
90
90
73
72.6
72
–90
–105
MAX
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd or 3rd Harmonic
70MHz Input
140MHz Input
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
70MHz Input
140MHz Input
l
75
75
77
l
84
84
85
S/(N+D)
Signal-to-Noise Plus
Distortion Ratio
Crosstalk, Near Channel
Crosstalk, Far Channel
5MHz Input
70MHz Input
140MHz Input
10MHz Input (Note 12)
10MHz Input (Note 12)
l
69.6
70.2
70.4
inTernal reFerence characTerisTics
PARAMETER
V
CM
Output Voltage
V
CM
Output Temperature Drift
V
CM
Output Resistance
V
REF
Output Voltage
V
REF
Output Temperature Drift
V
REF
Output Resistance
V
REF
Line Regulation
–400µA < I
OUT
< 1mA
1.7V < V
DD
< 1.9V
–600µA < I
OUT
< 1mA
I
OUT
= 0
CONDITIONS
I
OUT
= 0
The
l
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. A
IN
= –1dBFS. (Note 5)
MIN
0.5 • V
DD
– 25mV
TYP
0.5 • V
DD
±25
4
1.225
1.250
±25
7
0.6
1.275
MAX
0.5 • V
DD
+ 25mV
UNITS
V
ppm/°C
Ω
V
ppm/°C
Ω
mV/V
21754314fa
4
LTC2175-14/
LTC2174-14/LTC2173-14
DigiTal inpuTs anD ouTpuTs
SYMBOL PARAMETER
ENCODE INPUTS (ENC
+
, ENC
–
)
Differential Encode Mode (ENC
–
Not Tied to GND)
V
ID
V
ICM
V
IN
R
IN
C
IN
V
IH
V
IL
V
IN
R
IN
C
IN
V
IH
V
IL
I
IN
C
IN
R
OL
I
OH
C
OUT
V
OD
V
OS
R
TERM
Differential Input Voltage
Common Mode Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
Input Capacitance
High Level Input Voltage
Low Level Input Voltage
Input Current
Input Capacitance
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
Differential Output Voltage
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
Termination Enabled, OV
DD
= 1.8V
l
l
l
l
The
l
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. (Note 5)
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 8)
Internally Set
Externally Set (Note 8)
ENC
+
, ENC
–
to GND
(See Figure 10)
l
l
l
0.2
1.1
0.2
10
3.5
1.2
1.6
3.6
V
V
V
V
kΩ
pF
V
0.6
V
V
kΩ
pF
V
0.6
V
µA
pF
Ω
10
3
µA
pF
454
250
1.375
1.375
mV
mV
V
V
Ω
10
3
3.6
30
3.5
Single-Ended Encode Mode (ENC
–
Tied to GND)
V
DD
= 1.8V
V
DD
= 1.8V
ENC
+
to GND
(See Figure 11)
l
l
l
1.2
0
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
V
DD
= 1.8V
V
DD
= 1.8V
V
IN
= 0V to 3.6V
l
l
l
1.3
–10
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)
1 Introduction
In the mid-1960s, American scientist Maas conducted extensive experimental research on the charging process of open-cell batteries and proposed an acceptable charging curve for ...[详细]
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