IDT74LVC162827A
3.3V CMOS 20-BIT BUFFER WITH 5 VOLT TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS
20-BIT BUFFER
WITH 5 VOLT TOLERANT I/O
FEATURES:
DESCRIPTION:
IDT74LVC162827A
• Typical t
SK(o)
(Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• V
CC
= 3.3V ± 0.3V, Normal Range
• V
CC
= 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4µ W typ. static)
µ
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP, TSSOP, and TVSOP packages
DRIVE FEATURES:
APPLICATIONS:
• High Output Drivers: ±12mA
• Reduced system switching noise
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
The LVC162827A 20-bit buffer is built using advanced dual metal CMOS
technology. The 20-bit bus driver provides high-performance bus interface
buffering for wide data/address paths or busses carrying parity. Two pair
of NAND-ed output enable controls offer maximum control flexibility and are
organized to operate the device as two 10-bit buffers or one 20-bit buffer.
Flow-through organization of signal pins simplifies layout. All inputs are
designed with hysteresis for improved noise margin.
The LVC162827A buffer is ideally suited for driving high capacitance
loads and low impedance backplanes. The output buffers are designed with
power off disable capability to allow “live insertion” of boards when used as
backplane drivers.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVC162827A has been designed with a
±
12mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
FUNCTIONAL BLOCK DIAGRAM
1
OE
1
1
OE
2
1
56
2
OE
1
2
OE
2
28
29
1
A
1
55
2
1
Y
1
2
A
1
42
15
2
Y
1
TO NINE OTHER CHANNELS
TO NINE OTHER CHANNELS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 1999 Integrated Device Technology, Inc.
OCTOBER 1999
DSC-4947/1
IDT74LVC162827A
3.3V CMOS 20-BIT BUFFER WITH 5 VOLT TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
1
OE
1
1
Y
1
1
Y
2
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
V
TERM
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Continuous Clamp Current,
V
I
< 0 or V
O
< 0
Continuous Current through each
V
CC
or GND
–0.5 to +6.5
–65 to +150
–50 to +50
–50
±100
Unit
V
°C
mA
mA
mA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
OE
2
1
A
1
1
A
2
T
STG
I
OUT
I
IK
I
OK
I
CC
I
SS
GND
1
Y
3
1
Y
4
GND
1
A
3
1
A
4
V
CC
1
Y
5
1
Y
6
1
Y
7
V
CC
1
A
5
1
A
6
1
A
7
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
GND
1
Y
8
1
Y
9
1
Y
10
2
Y
1
2
Y
2
2
Y
3
GND
1
A
8
1
A
9
1
A
10
2
A
1
2
A
2
2
A
3
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
C
I/O
Parameter
(1)
Input Capacitance
Output Capacitance
I/O Port Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
V
IN
= 0V
Typ.
4.5
6.5
6.5
Max.
6
8
8
Unit
pF
pF
pF
NOTE:
1. As applicable to the device type.
GND
2
Y
4
2
Y
5
2
Y
6
GND
2
A
4
2
A
5
2
A
6
PIN DESCRIPTION
Pin Names
xOEx
xAx
xYx
Data Inputs
3-State Outputs
Description
Output Enable Inputs (Active LOW)
V
CC
2
Y
7
2
Y
8
V
CC
2
A
7
2
A
8
GND
2
Y
9
2
Y
10
2
OE
1
GND
2
A
9
2
A
10
2
OE
2
FUNCTION TABLE
(1)
Inputs
xOE
1
xOE
2
L
L
X
H
xAx
L
H
X
X
Outputs
xYx
L
H
Z
Z
SSOP/ TSSOP/ TVSOP
TOP VIEW
L
L
H
X
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
2
IDT74LVC162827A
3.3V CMOS 20-BIT BUFFER WITH 5 VOLT TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
A
= –40°C to +85°C
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
OFF
V
IK
V
H
I
CCL
I
CCH
I
CCZ
∆I
CC
High Impedance Output Current
(3-State Output pins)
Input/Output Power Off Leakage
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= 0V, V
IN
or V
O
≤
5.5V
V
CC
= 2.3V, I
IN
= –18mA
V
CC
= 3.3V
V
CC
= 3.6V
V
IN
= GND or V
CC
—
—
—
—
—
—
—
–0.7
100
—
—
—
±50
–1.2
—
10
10
500
µA
V
mV
µA
V
CC
= 3.6V
V
O
= 0 to 5.5V
—
—
±10
µA
Parameter
Input HIGH Voltage Level
Input LOW Voltage Level
Input Leakage Current
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 2.3V to 2.7V
V
CC
= 2.7V to 3.6V
V
CC
= 3.6V
V
I
= 0 to 5.5V
Test Conditions
Min.
1.7
2
—
—
—
Typ.
(1)
—
—
—
—
—
Max.
—
—
0.7
0.8
±5
µA
V
Unit
V
Quiescent Power Supply Current
Variation
3.6
≤
V
IN
≤
5.5V
(2)
One input at V
CC
- 0.6V, other inputs at V
CC
or GND
µA
NOTES:
1. Typical values are at V
CC
= 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
Parameter
Output HIGH Voltage
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
V
OL
Output LOW Voltage
V
CC
= 2.3V to 3.6V
V
CC
= 2.3V
V
CC
= 2.7V
V
CC
= 3V
Test Conditions
(1)
V
CC
= 2.3V to 3.6V
I
OH
= – 0.1mA
I
OH
= – 4mA
I
OH
= – 6mA
I
OH
= – 4mA
I
OH
= – 8mA
I
OH
= – 6mA
I
OH
= – 12mA
I
OL
= 0.1mA
I
OL
= 4mA
I
OL
= 6mA
I
OL
= 4mA
I
OL
= 8mA
I
OL
= 6mA
I
OL
= 12mA
Min.
V
CC
– 0.2
1.9
1.7
2.2
2
2.4
2
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
V
Unit
V
NOTE:
1. V
IH
and V
IL
must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate V
CC
range.
T
A
= – 40°C to + 85°C.
3
IDT74LVC162827A
3.3V CMOS 20-BIT BUFFER WITH 5 VOLT TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
OPERATING CHARACTERISTICS, V
CC
= 3.3V ± 0.3V, T
A
= 25°C
Symbol
C
PD
C
PD
Parameter
Power Dissipation Capacitance per Buffer/Driver Outputs enabled
Power Dissipation Capacitance per Buffer/Driver Outputs disabled
Test Conditions
C
L
= 0pF, f = 10Mhz
Typical
Unit
pF
—
—
SWITCHING CHARACTERISTICS
(1)
V
CC
= 2.7V
Symbol
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
SK
(o)
Parameter
Propagation Delay
xAx to xYx
Output Enable Time
xOEx to xYx
Output Disable Time
xOEx to xYx
Output Skew
(2)
1.5
10
1.5
8.5
500
ns
ps
1.5
11
1.5
9.5
ns
Min.
1.5
Max.
8
V
CC
= 3.3V ± 0.3V
Min.
1.5
Max.
6.5
Unit
ns
—
—
—
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. T
A
= – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC162827A
3.3V CMOS 20-BIT BUFFER WITH 5 VOLT TOLERANT I/O
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
Symbol
V
LOAD
V
IH
V
T
V
LZ
V
HZ
C
L
V
CC(1)
= 3.3V±0.3V
6
2.7
1.5
300
300
50
V
CC
500Ω
Pulse
(1, 2)
Generator
V
IN
D.U.T.
R
T
500Ω
C
L
LVC Link
V
CC(1)
= 2.7V
6
2.7
1.5
300
300
50
V
CC(2)
= 2.5V±0.2V
2 x Vcc
Vcc
Vcc / 2
150
150
30
Unit
V
V
V
mV
mV
pF
V
LOAD
Open
GND
SAME PHASE
INPUT TRANSITION
t
PLH
OUTPUT
t
PLH
OPPOSITE PHASE
INPUT TRANSITION
t
PHL
t
PHL
V
IH
V
T
0V
V
OH
V
T
V
OL
V
IH
V
T
0V
LVC Link
Propagation Delay
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
SWITCH
NORMALLY
CLOSED
LOW
t
PZH
OUTPUT
SWITCH
NORMALLY
OPEN
HIGH
V
LOAD/2
V
T
t
PHZ
V
T
0V
t
PLZ
DISABLE
V
IH
V
T
0V
V
LOAD/2
V
OL+
V
LZ
V
OL
V
OH
V
OH-
V
HZ
0V
LVC Link
V
OUT
Test Circuit for All Outputs
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
2. Pulse Generator for All Pulses: Rate
≤
10MHz; t
F
≤
2ns; t
R
≤
2ns.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
Enable and Disable Times
SWITCH POSITION
Test
Open Drain
Disable Low
Enable Low
Disable High
Enable High
All Other Tests
Switch
V
LOAD
GND
Open
V
IH
V
T
0V
V
OH
V
T
V
OL
V
OH
V
T
V
OL
t
PLH2
t
PHL2
LVC Link
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
SU
t
H
t
REM
t
SU
t
H
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
V
IH
V
T
0V
LVC Link
INPUT
Set-up, Hold, and Release Times
LOW-HIGH-LOW
PULSE
t
W
HIGH-LOW-HIGH
PULSE
V
T
LVC Link
t
PLH1
t
PHL1
OUTPUT 1
V
T
t
SK
(x)
t
SK
(x)
OUTPUT 2
t
SK
(x)
= t
PLH2
-
t
PLH1
or
t
PHL2
-
t
PHL1
Pulse Width
Output Skew - t
SK
(
X
)
NOTES:
1. For t
SK
(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For t
SK
(b) OUTPUT1 and OUTPUT2 are in the same bank.
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