Preliminary Data Sheet
May 2001
T8531A/T8532 Multichannel Programmable
Codec Chip Set
Features
s
s
s
Low-noise, balanced, receive SLIC interface
Few or no SLIC/codec interface components
required
Sigma-delta converters with dither noise reduction
Serial microcontroller control interface
Available in 64-pin MQFP and TQFP packages
Per-channel programmable gain and hybrid bal-
ance
s
s
s
s
Programmable termination impedances
Programmable
µ-law,
A-law, or linear PCM output
Tone plant:
— DTMF generator
— DTMF receiver
— Caller ID generator
— Call progress tones generator
Test utilities:
— Automatic gain calibration
— Tone generation
— dc generation
— dc measurement
— Variance computation
— Peak detection
Analog and digital loopbacks
Programmable time-slot assignment with bit offset
s
s
General Description
The multichannel programmable codec chip set is
comprised of the T8531A 16-channel line card signal
processor and one or two custom T8532 octal A/D
and D/A converters. A ROM-coded tone plant, with
line-test and self-test utilities, is included on the sig-
nal processor. Together these devices achieve a
highly integrated and highly programmable multi-
channel voice codec solution.
Software is provided to compute the gain and filter
coefficients required to program the codec.
s
s
s
VTX (8)
VRTX (8)
VRP (8)
VRN (8)
T8532
OCTAL
A/D
D/A
2
3
PCM
INTERFACE
VTX (8)
VRTX (8)
VRP (8)
VRN (8)
T8532
OCTAL
A/D
D/A
2
3
T8531A
DIGITAL
SIGNAL
PROCESSOR
ASIC
CK16
MICROPROCESSOR
INTERFACE
5-3793i (F)
Figure 1. System Block Diagram
T8531A/T8532 Multichannel Programmable
Codec Chip Set
Preliminary Data Sheet
May 2001
Table of Contents
Contents
Page
Contents
Page
Features ..................................................................... 1
General Description.................................................... 1
T8532 Description.................................................... 4
T8531A Description ................................................. 5
Pin Information ........................................................... 7
Chip Set Functional Description ............................... 12
Transmit Path......................................................... 12
Antialias Filter and
Σ-∆
Converter ...................... 12
Decimator ........................................................... 12
Digital Transmit Gain Adjustment........................ 12
Band Filtering ...................................................... 12
µ-Law,
A-Law, and Linear PCM Modes............... 12
Receive Path ......................................................... 13
Receive Path Filtering ......................................... 13
Digital Receive Gain............................................ 13
Interpolator and Digital Sigma-Delta
Modulator.......................................................... 13
Decoder, Filters, and Receive Amplifier ............. 13
Other Chip Set Functions....................................... 13
Voltage Reference............................................... 13
Hybrid Balance .................................................... 13
Analog Termination Impedance Synthesis.......... 13
Digital Termination Impedance Synthesis ........... 14
Loopback Modes ................................................. 14
Interchip Control Interface ................................... 14
T8531A Functional Blocks ..................................... 14
Clock Synthesizer................................................ 14
T8531A System Interface ................................... 15
T8531A Microprocessor Interface ....................... 15
T8532 Octal Control Interface ............................. 16
T8531A Time-Slot Assignment (TSA) ................. 16
DSP Engine Timing................................................ 16
T8531A Program Structure ................................. 16
Control of the DSP Engine via the
Microprocessor Interface .................................. 17
The DSP Engine Time-Slot Information
Tables ............................................................... 17
The DSP Engine ac Path Coefficient Table ........ 17
The Time-Slot Control Word................................ 18
Operations Performed by the DSP Engine at
T8531A Start-Up............................................... 18
Microprocessor Start-Up of the DSP Engine....... 19
Powering Up a Time Slot in the T8531................ 19
Disabling a Time Slot in the T8531 ..................... 19
T8532 Powerup/Powerdown ............................... 19
Changing DSP RAM Space of an Active
Time Slot........................................................... 20
DSP Engine Memory Requirements ................... 20
T8531A Reset and Start-Up................................... 20
Hardware Reset .................................................. 20
Internal Reset ...................................................... 21
Reset of the T8532 Devices ................................ 21
Start-Up After Internal Reset.................................. 21
Autocalibration..................................................... 22
User Test Features ................................................ 22
Off-Line Programmable System Test
Capability .......................................................... 22
On-Line Per-Channel Test Capability.................. 22
Inactive Mode with Loopback .............................. 22
Self-Test and Line-Test Routines .......................... 22
Tone Generation ................................................. 22
Tone Detection .................................................... 23
dc Generation...................................................... 23
dc Measurement.................................................. 23
Variance Computation......................................... 23
Peak Detection .................................................... 23
Tone Plant.............................................................. 23
DTMF Transceiver............................................... 23
Caller Line Identification ...................................... 23
Call Progress Tones............................................ 23
Absolute Maximum Ratings...................................... 24
Handling Precautions ............................................... 24
Electrical Characteristics .......................................... 25
dc Characteristics .................................................. 25
Transmission Characteristics ................................... 26
Timing Characteristics .............................................. 30
Software Interface .................................................... 33
Applications .............................................................. 44
Common Voltage Reference.................................. 47
Outline Diagrams...................................................... 48
64-Pin MQFP ......................................................... 48
64-Pin TQFP .......................................................... 49
Ordering Information................................................. 50
Appendix A. Transmit Path Group Delay vs. Bit
Offset ................................................................ 50
2
Agere Systems Inc.
Preliminary Data Sheet
May 2001
T8531A/T8532 Multichannel Programmable
Codec Chip Set
Table of Contents
(continued)
Figures
Page
Table 18. DSP Engine RAM Memory Map ................33
Table 19. T8531A Time-Slot Assignment Memory
Map ...........................................................35
Table 20A. Bit Map for T8531A Time-Slot Assignment
Registers at 0x1400—0x140F.................35
Table 20B. Bit Map for CTZ Disable and Null
Channel...................................................35
Table 21. T8531A Channel Register Memory Map
for T8532 Device 0 ...................................36
Table 22. T8531A Channel Register Memory Map
for T8532 Device 1 ...................................36
Table 23. Bit Map for T8532 Powerup/Powerdown
Registers at 0x1500—0x1507 and
0x1540—0x1547 .......................................37
Table 24. Bit Map for T8532 Channel Control
Register 1 at 0x1508—0x150F and
0x1548—0x154F .......................................37
Table 25. T8532 Control Register 1: Transmit
Gain ...........................................................37
Table 26. T8532 Control Register 1: Analog
Termination Impedance.............................37
Table 27. T8532 Control Register 1: Digital
Loopback ...................................................38
Table 28. Bit Map for T8532 All Channel Test
Register at 0x1510 and 0x1550.................38
Table 29. Bits 3:0 of T8532 All Channel Test
Register at 0x1510 and 0x1550.................38
Table 30. Bit Map for T8532 Channel Control
Register 2 at 0x1518—0x151F and
0x1558—0x155F .......................................39
Table 31. T8532 Control Register 2: Receive Gain ...39
Table 32. T8531A Control Register Map ...................39
Table 33. Bits 15:8 of T8531A Board Control Word 1
at 0x1FFE ..................................................40
Table 34. Bits 7:0 of T8531A Board Control Word 1
at 0x1FFE ..................................................40
Table 35. Bits 15:9 of T8531A Board Control Word 2
at 0x1FFC..................................................41
Table 36. Bits 8:0 of T8531A Board Control Word 2
at 0x1FFC..................................................41
Table 37. Bits 15:0 of T8531A Board Control Word 3
at 0x1FFA ..................................................41
Table 38. Bits 15:0 of T8531A Board Control Word 4
at 0x1FF8 ..................................................41
Table 39. Bits 15:0 of T8531A Board Control Word 5
at 0x1FF6 ..................................................41
Table 40. Bits 15:0 of T8531A Reset of
Microprocessor Commands at 0x7FFF .....41
Table 41. DSP Engine ROM Memory Map................42
Table 42. Transmit Path Group Delay vs. Bit Offset ..50
Figure 1. System Block Diagram .................................1
Figure 2. Block Diagram of T8532 Octal Converter.....4
Figure 3. Block Diagram of One T8532 Analog
Channel........................................................4
Figure 4. T8531A Block Diagram ................................5
Figure 5. T8531A Digital ac Path.................................6
Figure 6. Control, PCM, and Octal Interfaces..............6
Figure 7. T8532 64-Pin MQFP ....................................7
Figure 8. T8531A 64-Pin TQFP...................................9
Figure 9. Timing Characteristics of PCM Interface
Assuming 2.048 MHz SCK Rate ................31
Figure 10. Timing Diagram for Microprocessor
Write/Read to/from the DSP on the
Control Interface.......................................32
Figure 11. Line Card Solution Using the L7585
SLIC .........................................................44
Figure 12. Line Card Solution Using the L9215G
SLIC .........................................................45
Figure 13. Line Card Solution Using the L9310G
SLIC .........................................................46
Figure 14. Common 2.4 V Voltage Reference...........47
Tables
Page
Table 1. T8532 Pin Descriptions ................................. 8
Table 2. T8531A Pin Descriptions ............................. 10
Table 3. Active Time-Slot Spacing in a PCM
Bus Frame ................................................... 15
Table 4. DSP Engine RAM Map for Channel_0 ac
Path Coefficients ......................................... 17
Table 5A. Bit Map for DSP Engine Time-Slot
Control Word............................................. 18
Table 5B. Bit Map for Default Per-Board
Coefficient Tables...................................... 18
Table 6. DSP Engine RAM Map for Time-Slot
Information Table 0...................................... 18
Table 7. Summary of Microprocessor Commands
for Control of T8531A Data Processing....... 20
Table 8. Digital Interface............................................ 25
Table 9. Analog Interface .......................................... 25
Table 10. T8532 Power Dissipation...........................26
Table 11. T8531A Power Dissipation ........................ 26
Table 12. Gain and Dynamic Range ......................... 26
Table 13. Noise (per Channel) ..................................28
Table 14. Distortion and Group Delay ....................... 29
Table 15. Crosstalk.................................................... 29
Table 16. PCM Interface Timing ............................... 30
Table 17. Serial Control Port Timing ........................ 32
Agere Systems Inc.
3
T8531A/T8532 Multichannel Programmable
Codec Chip Set
Preliminary Data Sheet
May 2001
General Description
(continued)
T8532 Description
The T8532 block diagram is shown in Figure 2. Each of its eight channels consists of an antialias filter, sigma-delta
A/D and D/A converters, reconstruction and smoothing filters, termination impedance synthesis, and selectable
gain. The digital oversampled data is multiplexed onto a serial data port designed to interface with the T8531A
Another serial interface accepts control data from the T8531A for activating the various gain settings, self-test, and
powerdown modes. This chip also contains a precision voltage reference.
VTX[7:0]
VRTX[7:0]
VRP[7:0]
VRN[7:0]
8-CHANNEL
A/D D/A
ANALOG HYBRID
&
TERMINATION
OSDX[1:0]
OVERSAMPLED
DATA
INTERFACE
OSDR[1:0]
OSCK
OSFS
V
DDA
V
SSA
V
DD
V
SS
VOLTAGE
REFERENCE
CONTROL
INTERFACE
CDO
CDI
CCS
RSTB
5-3794.b (F)
Figure 2. Block Diagram of T8532 Octal Converter
DIGITAL LOOPBACK
VTX
VRTX
GAIN
AAF*
∑-∆
A/D
1.024 MHz
A
T
GAIN
V REFERENCES
VRP
VRN
SUM
GAIN
RECEIVE
FILTER
D/A
1.024 MHz
5-3796.d (F)
* Antialiasing filter.
Figure 3. Block Diagram of One T8532 Analog Channel
4
Agere Systems Inc.
Preliminary Data Sheet
May 2001
T8531A/T8532 Multichannel Programmable
Codec Chip Set
General Description
(continued)
T8531A Description
As shown in Figure 4, the T8531A contains a digital signal processor (DSP) engine surrounded by a customized
input/output (I/O) frame. The I/O frame performs the
µ-law
or A-law conversion as well as the decimation and inter-
polation functions needed to interface the sigma-delta bit streams to the digital signal processor engine. The
sigma-delta converters operate at a 1.024 MHz sample rate, while the signal processor operates at 16 ksamples/s.
A key function of the I/O frame is to control the timing of the digital data going to the signal processor so that group
delay is minimized.
The I/O frame also contains an integrated phase-locked loop which synthesizes all the required internal clocks for
the chip set.
The microcontroller interface is used to run the ROM routines and to download the gain, filter, and balance network
settings, powerup/powerdown commands, time-slot assignments, digital loopback settings, and commands for the
T8532 octal chips.
SDR
SDX
SYSTEM PCM INTERFACE
PLL
CLOCK
SYNTHESIZER
DATA TRANSFER
µ/A-LAW
CONVERTER
MICRO-
PROCESSOR
CONTROL
INTERFACE
UPCS
UPCK
JTAG
DIGITAL
SIGNAL
PROCESSING
ENGINE
DSP
ROM
UPDI
UPDO
HIGHZB
DSP
RAM
RSTB
T_SYNC
TSTCLK
TSA
DECIMATOR
INTERPOLATOR
TEST
V
DD
V
SS
T8532 OVERSAMPLED INTERFACE
T8532 CONTROL INTERFACE
HDS
SCK
SFS
STSXB
CCS0
TDO
TDI
TCK
TMS
CK16
V
DDA
V
SSA
CCS1
CDO
OSCK
OSFS
OSDX/R[3:0]
CDI
0505(F)
Figure 4. T8531A Block Diagram
Agere Systems Inc.
5
DSP 与 ARM 处理器
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