TS81102G0
8/10 bit – 2 GSPS 1:8/1:4 DEMUX
DESCRIPTION
The DEMUX is designed to fit with TCS high speed ADC
TS8387 and TS8388B and further G’core ADC 2 and
4GSPS family.
This DEMUX allows users to process the high speed out-
put data stream down to processor speed. It uses the very
high speed bipolar technology (25 GHz NPN cutt–off fre-
quency) B6HF from SIEMENS.
MAIN FEATURES
Programmable Demux ratio :
. 1:4 : Data Rate max=1GSPS,
P
D (8b/10b)
< 3.8 / 4.1 W
(ECL 50
W
output)
. 1:8 : Data Rate max=2GSPS,
P
D (8b/10b)
< 5.0/ 5.7 W
(ECL 50
W
output)
. 1:16 with 1 TS8388B and 2 DEMUX.
Parallel output mode.
8 /10 bit, with nap mode for the 2 unused bit.
ECL Differential input data.
DataReady or DataReady/2 input clock.
Input clock sampling delay adjust.
Single ended output data :
. Adjustable common mode and swing
. Logic threshold reference output
. (ECL, PECL, TTL).
Asynchronous reset.
Synchronous reset
(to be confirmed).
ADC + DEMUX multi–channel applications :
. Stand–alone delay adjust cell for ADCs sampling
instant alignment
Differential data ready output.
Built–in self test (BIST).
Dual supply V
EE
= –5 V, Vcc = +5 V,
Radiation tolerance oriented design (more than 100Krad
(Si) expected).
– Hermetic package :
CI–CGA 360 on request only
– Package : TBGA 240
Tape Ball Grid Array (cavity down)
SCREENING
TCS standard screening level.
Mil–PRF–38535, QML level Q (TBC) for CI–CGA package
only (TBC)
Space screening level according to ESA/SCC 9000 (TBC)
for CI–CGA package only.
Temperature range :
0°C < Tc < +70
°C
–40°C <Tc < +85°C
September 1999
Rev. 1
1/30
TS81102G0
Table of Contents
1. BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. MAIN FUNCTIONS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1. Programmable Demux ratio : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2. Parallel output mode : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.3. Input clock sampling delay adjust : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.4. Asynchronous reset : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.5. ADC + DEMUX mono–channel applications : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.6. ADC + DEMUX multi–channel applications with asynchronous reset : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.7. Synchronous Reset (to be confirmed) : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.8. ADC + DEMUX multi–channel applications with synchronous reset (to be confirmed) :
5
2.9. 1:16 conversion ratio : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.10.Counter programmable state : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.11. Pipeline delay : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.12.8 /10 bit, with nap mode for the 2 unused bit : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.13.ECL Differential input data : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.14.50 ohms Differential output data : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.15.Single ended output data : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.16.Differential Data Ready output : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.17.Built–in Self Test (BIST). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1. ABSOLUTE MAXIMUM RATINGS (see note below) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2. RECOMMENDED CONDITIONS OF USE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.3. ELECTRICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4. SWITCHING PERFORMANCE AND CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.5. EXPLANATION OF TEST LEVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4. PACKAGE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.2. TBGA 240 package – Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3. Outline dimensions – 240 Tape Ball Grid Array. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.4. Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5. APPLYING THE TS81102G0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6. DEFINITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7. ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2/30
TS81102G0
1. BLOCK DIAGRAM
Data Path
DEMUXDelAdjCtrl
SwiAdj
VplusDOut
VCC
GND
VEE
DIODE
Clock Path
(to be confirmed)
SyncReset
AsyncReset
ADCDelAdjIn
ADCDelAdjCtrl
delay
ClkInType
RatioSel
FS/8
NAP
delay
B
2
BIST
8/10
mux
8/10
ClkPar
even
master
latch
even
slave
latch
odd
master
latch
odd
slave
latch
Phase
control
RstGen
Reset
mux
Counter
(8 stage
shift register)
8
ClkIn
8
Counter
Status
Latch Sel Even/Odd [1..8/10]
Port Selection Clock
8
FS/8
8
Data
Output
Clock
1
8/10
3
RatioSel
I[0..7/9]
NbBit
BIST
A[0..7/9]
RefA
C[0..7/9]
RefC
E[0..7/9]
RefE
G[0..7/9]
RefG
B[0..7/9]
RefB
D[0..7/9]
RefD
F[0..7/9]
RefF
H[0..7/9]
RefH
DataReady
generation
Even Ports
Odd Ports
DR/DR
3/30
ADCDelAdjOut
TS81102G0
2. MAIN FUNCTIONS DESCRIPTION
2.1. Programmable Demux ratio :
2.4. Asynchronous reset :
The conversion ratio is programmable :1:4 or 1:8.
Input Words :
1,2,3,4,5,6,7,8,...
1:4
Output Words :
PortA
PortB
PortC
PortD
PortE
PortF
PortG
PortH
Input Words :
1,2,3,4,5,6,7,8,...
1:8
1
2
3
4
5
6
7
...
The DEMUX can be asynchronously reseted to a pro-
grammable state depending on the conversion ratio. The
clock has to be stopped during reset. The output data are
ok after a number of input clock corresponding to the pipe-
line delay (see Pipeline Delay).
8
not used
not used
not used
not used
CLKIN
AsyncReset
Port A Selected
Port B selected
Port C selected
Output Words :
PortA
PortB
PortC
PortD
PortE
PortF
PortG
PortH
1
2
3
4
5
6
7
8
9 ...
10
11
12
13
14
15
16
Port D selected
Port E selected
Port F selected
Port G selected
Port H selected
2.5. ADC + DEMUX mono–channel applications :
Clock enable
D
CP
Q
2.2. Parallel output mode :
Parallel Mode :
ClkIn
DR
PortA
PortB
PortC
PortD
PortE
PortF
PortG
PortH
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
Master clock
Fs
Clk
Data
Signal
ADC
DR
Rst
Asynchronous reset
8
8
8
8
8
DEMUX 8
8
delay
8
Rst
8
Clk
ASIC
2.3. Input clock sampling delay adjust :
The input clock phase can be adjusted with an adjustable
delay of
250 ps. This is to ensure a good phase between
clock and data inside the DEMUX.
4/30
An acquisition channel can be constituted with a high
speed ADC, a DEMUX, and some ASICs. The high speed
ADC may be one of TCS family : TS8387, TS8388B. The
DEMUX is designed to slow down output data frequency
from the ADC, in order to allow the following ASIC to pro-
cess calculations on these data. The state of the DEMUX
and the ADC is controlled with the asynchronous reset.
The master clock is stopped with the clock enable, then the
reset pulse is sent to all the devices. Thus, their state is
controlled. Then, the master clock is released.
TS81102G0
2.6. ADC + DEMUX multi–channel applications with
asynchronous reset :
If the DEMUX was not synchronized with SyncReset, then
the output data and data Ready of the DEMUX are
changed. The output data are correct after a number of
input clock corresponding to the pipeline delay (see Pipe-
line Delay).
Clock enable
Master clock
D
CP
Q
Low Skew
FS
DR/2
8
8
delay 8
8
DEMUX 8
8
8
delay
Rst
8
Clk
SyncReset = FS/8
Internal reset
pulse
Port A Selected
Fs
Clk
Data
Signal 1
ADC
DR
Rst
Async. Rst
8
ASIC
Port B selected
Port C selected
Port D selected
Port E selected
Port F selected
Clk
Data
Signal 2
ADC
DR
Rst
8
8
8
delay 8
8
DEMUX 8
8
8
delay
Rst
8
Clk
Port G selected
Port H selected
ASIC
2.8. ADC + DEMUX multi–channel applications with syn-
chronous reset
(to be confirmed)
:
The synchronous reset can be used in mono–channel
applications where stopping FS is not possible or not easy
to do. It can also be used in multi–channel applications,
and is a simple way to synchronize these different chan-
nels as far as propagation delay of the various clocks is
correctly controlled.
8
8
8
8
DEMUX 8
8
delay
8
SyncRst 8
Clk
The DEMUX is designed so that several channels can
work together. A stand–alone delay adjust ( 250 ps) is
available in the DEMUX to set the phase of the sampling
clocks of the ADCs. The state of each DEMUX and each
ADC is controlled with the asynchronous reset. The mas-
ter clock is stopped with the clock enable, then the reset
pulse is sent to all the devices. Thus, their state is con-
trolled. Then, the master clock is released.
2.7. Synchronous Reset
(to be confirmed)
:
8
Data
Signal 1
ADC
DR
Clk
The DEMUX can be synchronously reseted to a program-
mable state depending on the conversion ratio. The clock
must not be stopped during reset. The synchronization
signal is a clock (SyncReset) which frequency is like
FS/8*n where n is a integer (n=1,2,3,...) in 1:8 mode and
FS/4*n in 1:4 mode. The division factor is called N in next
schematic. The Front edge of this clock is synchronized
with ClkIn inside the DEMUX, and generates a 200ps reset
pulse. This reset pulse occurs during a fixed level of ClkIn.
If the DEMUX was synchronized with SyncReset previous
to the reset, then the output data are immediately correct,
no modification can be seen at the output of the DEMUX,
and no data are lost.
FS
Divide
by N
Delay
Adjust
SyncReset
Clk
Data
Signal 2
ADC
DR
Rst
8
8
8
SyncRst 8
8
DEMUX 8
8
delay
8
8
Clk
5/30
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