TH7106
Low power 300 to 500MHz FSK Transmitter
Description
The TH7106 is a low power FSK transmitter
designed to operate at transmit frequencies
between 300 and 500MHz. It comprises a fre-
quency synthesizer and modulator to accept a
simple CMOS digital data input and generate an
FSK modulated output. Output power can be
adjusted to a maximum of 2 dBm.
The TH7106 has been optimised for use in
battery-powered applications with low current
consumption in both transmit and standby
modes.
Features
q
very low current consumption in transmit mode
q
very low standby current - typically a few
nanoamperes
q
wide power supply range: 2.6V to 4.8V
q
conforms to requirements of ETSI-300-220,
MPT1340 and FCC Part 15
q
very easy to use with low external component
count and cost
q
no discrete external inductors required
q
adjustable output power level
q
wireless office and home security systems
q
key-fob car security/central locking
q
low power telemetry
q
radio data transmission
q
consumer remote control units
Applications
Block diagram
VCC
VEE1
VEE2
VSUB
PS
SBY
OUT2
BYPS
crystal
oscillator
divide-
by-
64
P.A.
OUT1
VCO
RO1
RO2
phase
detector
buffer
DATA
charge
pump
LF
Figure 1: Block Diagram
VEE
Rev. 2.0
October 1997
TH7106 FSK Transmitter
Theory of
operation
The TH7106 comprises three main elements:
1
Input buffer and modulator
2
Frequency synthesizer for generation of the RF
output carrier from a low frequency external
crystal
3
Power amplifier for driving an external antenna
The IC accepts a digital CMOS input, and
modulates a fixed amplitude RF carrier in
frequency according to the digital input level.
The RF carrier is generated by the on-chip
phase locked loop (PLL) frequency synthesizer.
This contains a fixed divider which ensures that
the RF output frequency is 64 times the crystal
reference frequency. The power amplifier
provides a variable output level of up to 2 dBm
of output power depending upon the value of an
external resistor RI.
The PA has balanced outputs
OUT1
and
OUT2
which are in open collector configuration.
A balanced output is used since it provides
a high degree of suppression of even-order
harmonics of the fundamental. Odd order
harmonic suppression is achieved using on-
chip cancellation techniques.
Electrical
characteristics
Table 1: Absolute maximum ratings
Parameter
Supply voltage
Input voltage - Logic Inputs
Input Current - Logic Inputs
Storage temperature
Junction temperature
DATA & SBY pins
DATA & SBY pins
Conditions
Symbol
VCC
Min
-0.3
-0.3 V
-1.0
-40
-40
Max
+7.0
VCC + 0.3V
+1.0
150
150
mA
°C
°C
Unit
V
Table 2: Operating conditions
@ 434 MHz; @ 318 MHz
Parameter
Supply voltage
Ambient temperature
Symbol
VCC
Ta
Min
2.6
-40
Max
4.8
65
Unit
V
°C
Note:
All specification parameters guaranteed only with the following components
(please refer to figure 2 for application circuit):
RF transformer
Crystal
Mini-Circuits TC4-14
Euroquartz B537 6.78-MHz crystal (Cicad = 10 pF)
R1 = 3.9 k R2 = 3.3 k C7 = 1 nF C8 = 47 pF C1 = C2 = 22 pF
Table 3: DC Characteristics at 3.0V VCC and 23ºC ambient temperature
all parameters 100% production tested under these conditions unless otherwise stated
Parameter
Standby Current
Supply Current
DATA logic high level
DATA logic low level
DATA input current
Bias voltage on pin PS
Conditions
SBY = low
including open-collector output
currents
guaranteed by design
guaranteed by design
guaranteed by design
-0.3 < Vin < VCC+0.3
guaranteed by design
I(PS) = 100 µA
Symbol
Iccstb
Icclow
Vhigh
Vlow
Idata
V(PS)
0.7*VCC
-0.3V
-10
0.4
Min
Typ
0.1
Max
1
25
VCC+0.3
0.3*VCC
+10
µA
V
Unit
µA
mA
2
TH7106 FSK Transmitter
Electrical
characteristics
(continued)
Table 4: AC Characteristics at 3.0V VCC and 23ºC ambient temperature,
fc = 433.92 MHz, unless otherwise stated
all parameters 100 % production tested under these conditions unless otherwise stated
Parameter
Maximum Carrier
Frequency
Minimum Carrier Frequency
Maximum Data Rate
received BER<1% with
receiver pre-detection
bandwidth matched to data
rate
static peak-to peak value:
crystal and system dependent
static peak-to peak value:
crystal and system dependent
guaranteed by design,
external crystal
with R1=3.9 kOhms
Conditions
Symbo
fcmax
fcmin
Rmfsk
200
Min
440
290
Typ
Max
Unit
MHz
MHz
kbits/s
Frequency Deviation
(TH7106 in SOP)
Frequency Deviation
(TH7106 in SSOP)
Reference Frequency
Output Power
2nd Harmonic
3rd Harmonic
Reference Spurious
Phase Noise
VCO gain
Phase detector gain
∆
f
∆
f
fref
4.5
20
22
7.0
0.5
-34
-35
-45
-75
125
16
-29
-28
-40
kHz
kHz
MHz
dBm
dBc
dBc
dBc
dBc/Hz
MHz/V
µA/rad
∆
Po
∆
P2
∆
P3
at fc + (fref to 3fref)
guaranteed by design,
at 10 kHz offset
guaranteed by design
guaranteed by design
Pref
PN
KVCO
KPD
Matching
network and
antenna options
VCC
50 Ohms
1+1:1
1 OP1
2 VEE1
3 PS
4 SBY
DATA
OP2 16
VEE 15
C8
R1
SBY
14
C7
13
BYPS 12
R2
C6
5 DATA
6 VEE2
VCC
VCC 11
VCC
C5
7 VCC1
8 RO1
VSUB 10
RO2
9
C1
X1
C2
Figure 2: Application Diagram
3
TH7106 FSK Transmitter
Matching
network and
antenna options
(continued)
Figure 2 shows a typical application diagram.
In order to minimise second harmonic distortion,
a differential output configuration is recom-
mended. The TH7106 needs the following:
1) a dc bias reference to VCC (preferrably through
direct connection of a loop antenna connected
to VCC at its centre, or use of printed bias
inductors with a connection to VCC). Thesys’
TH710X series of evaluation boards provide
large and small loop antenna solutions for cus-
tomers to copy. These boards require a minimum
number of external components, and importantly
no
discrete inductors are required. For driving an 3) the PLL synthesizer is designed to operate with
an external second order loop as shown in
external single-ended antenna, a high efficiency
figure 2, with component values as shown in
printed balun is also available.
Table 7. These values determine the loop
For optimum operation, the following points are
bandwidth and dynamics and operation of the
highlighted:
loop is not guaranteed for any other values
1) The IC can provide 7.5mA of current into the load
4) The bias current for the power amplifier directly
2) for maximum output power, it is recommended
controls the output current and hence the O/P
that the antenna load be transformed to an
power. This bias current is set by an external
impedance of 200Ohms (RPS is set at
resistor connected between
PS
and ground.
3.9kOhms)
Output power versus RI values is shown in
Table 5, for a differential load impedance of 200
Ω.
Table 5: Output Power Settings
R
Output power
(kOhms)
(dBm)
2.8
2
3.8
0
5.2
-2
6.7
-4
8.5
-6
9.7
-8
10.3
-10
10.7
-12
Current cons.
(mA)
25
22
20
19
18
17
16
16
Frequency
deviation
The amount of frequency deviation depends
upon the type of external crystal used. An on-
chip capacitor of 3pF is switched in parallel
with the crystal to shift its frequency of operation.
For instance, on the TH710X series of evalua-
tion boards, the peak-to-peak frequency
deviation possible with the supplied crystal is
over 15kHz in SOP packaged parts and 25 kHz
for SSOP packaged parts. The crystal param-
eters are specified as shown aside:
For smaller frequency deviations, then a less
pullable crystal can be specified (eg 20 pF or
30 pF load crystals are less pullable). If peak-to-
peak frequency deviations of much greater than
15kHz are required, then please consult Thesys
for information on how to achieve this.
Table 6 - Crystal specifications
Supplier/part number
Euroquartz: B537
Tel.:
0044146076477
6.78 MHz
HC49/U
AT
+/-10 ppm
+/-10 ppm
-10 to + 60°C
10 pF
50 Ohms
5 pF
20 fF
40 ppm/pF
Frequency
Package
Operating mode
Calibration tolerance
Temperature stability
Operating temp range
Circuit loading
Maximum ESR, R1
Static capacitance (typical), Co
Motional capacitance (typical), C1
Pullability
External
components
Table 7: Recommended External Components
Component
C1
C2
C5
C6
C7
C8
R1
R2
X1
Crystal Oscillator
Crystal Oscillator
Supply Decoupling
Regulator Decoupling
PLL Loop Filter
PLL Loop Filter
O/P power set
PLL Loop Filter
Crystal
Function
Value
22 pF
22 pF
100
100
1
47
3.9
3.3
6.78
Tolerance
± 5%
± 5%
± 20%
± 20%
± 5%
± 5%
± 5%
± 5%
< 20ppm
Units
pF
pF
nF
nF
nF
pF
kOhms
kOhms
MHz
4
TH7106 FSK Transmitter
I/O interfacing
Table 8: I/O interfacing
No.
1
2
3
4
5
6
8
9
10
11
12
13
15
16
Signal
OP1
VEE1
PS
SBY
DATA
VEE2
RO1
RO2
VSUB
VCC
BYPS
LF
VEE
OP2
Description
PA Output
Ground (0V)
Power Set
Standby (complete power down)
Data
Ground (0V)
Reference Oscillator (emitter)
Reference Oscillator (base)
Substrate Connection (0V)
Supply (Battery)
Power supply decoupling to ground
Low Pass Filter
Ground (0V)
PA Output (complement)
Input and output
interface
diagrams
+VCC
+
400 mV
-
OP1
OP2
+ VCC
LF1
from
modulator
∅
= 7.5 mA
+ VCC
+ VCC
25kΩ
RO2
DATA
SBY
RO1
P.A.
VBIAS
RI
Figure 3: Input and output interface diagrams
5
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