NCP81105, NCP81105H
DrMOS Supporting, 1/2/3
Phase Power Controller
with SVID Interface for
Desktop and Notebook
VR12.5 & VR12.6 CPU
Applications
The NCP81105 is a DrMOS supporting controller optimized for
Intel® VR12.5 & VR12.6 compatible CPUs. The controller combines
true differential voltage sensing, differential inductor DCR current
sensing, input voltage feed−forward, and adaptive voltage positioning
to provide accurately regulated power for both Desktop and Notebook
CPU applications. The control system is based on Dual−Edge
pulse−width modulation (PWM), to provide the fastest initial response
to dynamic load events plus reduced system cost. The NCP81105 is
compatible with DrMOS type power stages such as NCP5367,
NCP5368, NCP5369 and NCP5338.
The NCP81105’s output can be configured to operate in single phase
during light load operation
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improving overall system efficiency. A
high performance operational error amplifier is provided to simplify
compensation of the system. Patented Dynamic Reference Injection
further simplifies loop compensation by eliminating the need to
compromise between closed−loop transient response and Dynamic
VID performance. Patented Total Current Summing provides highly
accurate current monitoring for droop and digital current monitoring.
Features
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36
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MARKING
DIAGRAM
1
NCP
81105
AWLYYWWG
QFN36
CASE 485CC
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 35 of this data sheet.
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Meets Intel’s VR12.5 Specifications
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Implements VR12.6 PS4 State and SVID Reporting
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Mixed Voltage/Current Mode, Dual Edge Modulation
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for Fastest Initial Response to Transient Loading
High Impedance Differential Voltage Amplifier
High Performance Operational Error Amplifier
High Impedance Total Current Sense Amplifier
True Differential Current Sense Amplifiers for
Balancing Current in Each Phase
Digital Soft Start Ramp
Dynamic Reference Injection
Accurate Total Summing Current Amplifier
“Lossless” Inductor DCR Current Sensing
Summed, Thermally Compensated Inductor Current
Sensing for Adaptive Voltage Positioning (AVP)
48 mV/ms Fast Output Slew Rate (NCP81105)
10 mV/ms Fast Output Slew Rate (NCP81105H)
Programmable Slow Slew Rates as a Fraction of Fast
Slew Rate
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Reduced Enable to First SVID Command Latency
Phase−to−Phase Dynamic Current Balancing
Switching Frequency Range of 280 kHz to 1.5 MHz
Starts up into Pre−Charged Loads while Avoiding False
OVP
Compatible with DrMOS Power Stages
Power−saving Phase Shedding
Vin Feed−forward Ramp Slope Compensation
Pin Programming for Internal SVID parameters
Output Over Voltage Protection (OVP) & Under
Voltage Protection (UVP)
Over Current Protection (OCP)
Power Good Output with Internal Delays
This is a Pb−Free Device
Applications
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Desktop and Notebook Microprocessors
©
Semiconductor Components Industries, LLC, 2013
October, 2013
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Rev. 2
1
Publication Order Number:
NCP81105/D
NCP81105, NCP81105H
PIN LIST AND DESCRIPTION
Pin
No.
1
2
3
4
5
6
7
8
9
10
Symbol
EN
VCC
VR_HOT#
SDIO
ALERT#
SCLK
ROSC
VR_RDY
TSENSE
OD#
Description
Logic input. Logic high enables the NCP81105 and logic low disables it.
Power for the internal control circuits. A decoupling capacitor must be connected from this pin to ground.
Open drain (logic level) output for over−temperature reporting. Low indicates high temp.
Bidirectional Serial VID data interface.
Open drain Serial VID ALERT# output.
Serial VID clock input.
This pin outputs a constant current. A resistance from this pin to ground programs the switching fre-
quency.
Open drain output. High indicates that the NCP81105 is regulating the output.
Temperature sense input.
Phase Disabling Output, tied to the Enable, SMOD or ZCD_EN# pin of phases 2 and 3 DrMOS. Except
in PS0 mode, this output pulls low to disable the DrMOS if connected to an enable input. If connected to
a DrMOS SMOD or ZCD_EN# input, both HS & LS FETs are held off since PWM2 & PWM3 are also low.
Actively pulls high in PS0 mode.
Phase 1 Zero Cross Detection (ZCD) disable output. In PS2 & PS3, SMOD pulls LOW when phase 1
inductor current is negative to perform (or allow the DrMOS ZCD function to perform) diode emulation,
and pulls HIGH when phase 1 inductor current is positive. In PS0 & PS1, SMOD stays high to force the
phase 1 DrMOS into Continuous Conduction.
PWM output to Phase 2 DrMOS
PWM output to Phase 3 DrMOS
PWM output to Phase 1 DrMOS
Enable output for DrMOS
During startup, a resistor from this pin to ground programs ICC_MAX.
During startup, a resistor from this pin to ground programs the low frequency compensator pole of the
NCP81105 voltage control feedback loop.
Positive input to phase 1 current sense amplifier for balancing phase currents
Negative input to phase 1 current sense amplifier
Positive input to phase 3 current sense amplifier for balancing phase currents
Negative input to phase 3 current sense amplifier
Positive input to phase 2 current sense amplifier for balancing phase currents
Negative input to phase 2 current balance sense amplifier
Non−inverting input for the total output current sense amplifier. Also, the absolute OVP input.
Inverting input of total output current sense amplifier.
Output of total output current sense amplifier.
Input to program the over−current shutdown threshold.
Total current monitor output. A resistor from this pin to ground calibrates SVID output current reporting.
VDC applied to this pin provides feed−forward compensation for the pulsewidth modulator. The current
into this pin controls the slope of PWM ramp. A low voltage on this pin will inhibit NCP81105 startup.
During startup, a resistor from this pin to ground programs the BOOT voltage
During startup, a resistor from this pin to ground programs the scaling of the output Droop with respect to
the total output current signal produced between CSCOMP and CSREF.
Output of the error amplifier.
Error amplifier voltage feedback input.
Output of the differential remote sense amplifier.
Inverting input to the differential remote sense amplifier (VSS sense).
Non−inverting input to the differential remote sense amplifier (VCC sense).
Power supply return (QFN Flag)
11
SMOD
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
PWM2
PWM3
PWM1
DRVON
IMAX
INT_SEL
CSP1
CSN1
CSP3
CSN3
CSP2
CSN2
CSREF
CSSUM
CSCOMP
ILIM
IOUT
VRMP
VBOOT
DGAIN
COMP
FB
DIFFOUT
VSN
VSP
GND
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