NCP81071
Dual 5 A High Speed
Low-Side MOSFET Drivers
with Enable
NCP81071 is a high speed dual low−side MOSFETs driver. It is
capable of providing large peak currents into capacitive loads. This
driver can deliver 5 A peak current at the Miller plateau region to help
reduce the Miller effect during MOSFETs switching transition. This
driver also provides enable functions to give users better control
capability in different applications. ENA and ENB are implemented
on pin 1 and pin 8 which were previously unused in the industry
standard pin−out. They are internally pulled up to driver’s input
voltage for active high logic and can be left open for standard
operations. This part is available in MSOP8−EP package, SOIC8
package and WDFN8 3 mm x 3 mm package.
Features
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MARKING
DIAGRAMS
8
SOIC−8
D SUFFIX
CASE 751
XXXX
ALYW
G
1
•
•
•
•
•
•
•
High Current Drive Capability
±5
A
TTL/CMOS Compatible Inputs Independent of Supply Voltage
Industry Standard Pin−out
High Reverse Current Capability (6 A) Peak
Enable Functions for Each Driver
8 ns Typical Rise and 8 ns Typical Fall Times with 1.8 nF Load
Typical Propagation Delay Times of 20 ns with Input Falling and
20 ns with Input Rising
•
Input Voltage from 4.5 V to 20 V
•
Dual Outputs can be Paralleled for Higher Drive Current
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Applications
MSOP−8
Z SUFFIX
CASE 846AM
1
1
XXXX
AYW
G
WDFN8
MN SUFFIX
CASE 511CD
XX
A
L
Y
W
M
G
XX MG
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
•
•
•
•
•
•
•
•
Server Power
Telecommunication, Datacenter Power
Synchronous Rectifier
Switch Mode Power Supply
DC/DC Converter
Power Factor Correction
Motor Drive
Renewable Energy, Solar Inverter
(Note: Microdot may be in either location)
PIN CONNECTIONS
1
ENA
INA
GND
INB
(Top View)
8
ENB
OUTA
VDD
OUTB
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
©
Semiconductor Components Industries, LLC, 2016
1
April, 2016 − Rev. 3
Publication Order Number:
NCP81071/D
NCP81071
VDD
ENA
Ref
VDD
INA
Ref
VDD
ENB
Ref
VDD
INB
Ref
NCP81071A
VDD
ENA
Ref
VDD
INA
Ref
VDD
ENB
Ref
Logic
B Channel
INB
Ref
NCP81071C
GND
Logic
A Channel
VDD
UVLO
VDD
OUTB
VDD
OUTA
VDD
VDD
Logic
B Channel
GND
INB
Ref
NCP81071B
Logic
A Channel
VDD
UVLO
VDD
OUTB
ENB
Ref
Logic
B Channel
GND
VDD
OUTA
INA
Ref
VDD
VDD
VDD
ENA
Ref
Logic
A Channel
VDD
UVLO
VDD
OUTB
VDD
OUTA
VDD
VDD
VDD
Figure 1. NCP81071 Block Diagram
Table 1. PIN DESCRIPTION
Pin No.
1
Symbol
ENA
Description
Enable input for the driver channel A with logic compatible threshold and hysteresis. This pin is used to en-
able and disable the driver output. It is internally pulled up to VDD with a 200 kW resistor for active high op-
eration. The output of the pin when the device is disabled will be always low.
Input of driver channel A which has logic compatible threshold and hysteresis. If not used, this pin should be
connected to either VDD or GND. It should not be left unconnected.
Common ground. This ground should be connected very closely to the source of the power MOSFET.
Input of driver channel B which has logic compatible threshold and hysteresis. If not used, this pin should be
connected to either VDD or GND. It should not be left unconnected.
Output of driver channel B. The driver is able to provide 5 A drive current to the gate of the power MOSFET.
Supply voltage. Use this pin to connect the input power for the driver device.
Output of driver channel A. The driver is able to provide 5 A drive current to the gate of the power MOSFET.
Enable input for the driver channel B with logic compatible threshold and hysteresis. This pin is used to en-
able and disable the driver output. It is internally pulled up to VDD with a 200 kW resistor for active high op-
eration. The output of the pin when the device is disabled will be always low.
2
3
4
5
6
7
8
INA
GND
INB
OUTB
VDD
OUTA
ENB
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2
NCP81071
TYPICAL APPLICATION CIRCUIT
NCP81071
ENA
INA
1
8
ENB
OUTA
2
7
VDD
GND
3
6
OUTB
4
5
INB
Table 2. ABSOLUTE MAXIMUM RATINGS
Value
Min
Supply Voltage
Output Current (DC)
Reverse Current (Pulse< 1
ms)
Output Current (Pulse < 0.5
ms)
Input Voltage
Enable Voltage
Output Voltage
Output Voltage (Pulse < 0.5
ms)
Junction Operation Temperature
Storage Temperature
Electrostatic Discharge
Iout_pulse
INA, INB
ENA, ENB
OUTA, OUTB
OUTA, OUTB
T
J
T
stg
Human body model, HBM
Charge device model, CDM
OUTA OUTB Latch−up Protection
−6.0
−0.3
−0.3
−3.0
−40
−65
4000
1000
500
mA
6.0
VDD+0.3
VDD+0.3
VDD+0.3
VDD+3.0
150
160
V
V
V
°C
VDD
Iout_dc
−0.3
0.3
6.0
Max
24
Unit
V
A
A
A
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 3. RECOMMENDED OPERATING CONDITIONS
Parameter
VDD supply Voltage
INA, INB input voltage
ENA, ENB input voltage
Junction Temperature Range
Rating
4.5 to 20
−5.0 to VDD
0 to VDD
−40 to +140
Unit
V
V
V
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 4. THERMAL INFORMATION
Package
SOIC−8
MSOP−8 EP
WDFN8 3x3
q
JA
(5C/W)
115
39
39
q
JC
(5C/W)
50
4.7
4.7
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3
NCP81071
Table 5. INPUT/OUTPUT TABLE
NCP81071A
ENA
H
H
H
H
L
Any
x (Note 1)
x (Note 1)
x (Note 1)
x (Note 1)
ENB
H
H
H
H
L
Any
x (Note 1)
x (Note 1)
x (Note 1)
x (Note 1)
INA
L
L
H
H
Any
x (Note 1)
L
L
H
H
INB
L
H
L
H
Any
x (Note 1)
L
H
L
H
OUTA
H
H
L
L
L
L
H
H
L
L
OUTB
H
L
H
L
L
L
H
L
H
L
NCP81071B
OUTA
L
L
H
H
L
L
L
L
H
H
OUTB
L
H
L
H
L
L
L
H
L
H
NCP81071C
OUTA
H
H
L
L
L
L
H
H
L
L
OUTB
L
H
L
H
L
L
L
H
L
H
1. Floating condition, internal resistive pull up or pull down configures output condition
PRODUCT MATRIX
NCP81071A
NCP81071B
NCP81071C
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NCP81071
Table 6. ELECTRICAL CHARACTERISTICS
Parameter
SUPPLY VOLTAGE
VDD Under Voltage Lockout (rising)
VDD Under Voltage Lockout
(hysteresis)
Operating Current (no switching)
V
CCR
V
CCH
I
DD
INA = 0, INB = 5 V, ENA = ENB = 0
INA = 5 V, INB = 0, ENA = ENB = 0
INA = 0, INB = 5 V, ENA = ENB = 5 V
INA = 5 V, INB = 0, ENA = ENB = 5 V
VDD rising
VDD rising
3.5
4.0
400
1.4
3
4.5
V
mV
mA
(Typical values: V
DD
=12 V, 1
mF
from V
DD
to GND, T
A
= T
J
= −40°C to 140°C, typical at T
AMB
= 25°C, unless otherwise specified)
Symbol
Test Conditions
Min
Typ
Max
Units
VDD Under Voltage Lockout to Output
Delay (Note 2)
INPUTS
High Threshold
Low Threshold
INA, INB Pull−Up Resistance
INA, INB Pull−Down Resistance
OUTPUTS
Output Resistance High
Output Resistance Low
Peak Source Current (Note 3)
Miller Plateau Source Current (Note 3)
Peak Sink Current (Note 3)
Miller Plateau Sink Current (Note 3)
ENABLE
High−Level Input Voltage
Low−Level Input Voltage
ENA, ENB pull−up resistance
Propagation Delay Time (EN to OUT)
(Notes 2, 4)
Propagation Delay Time (EN to OUT)
(Notes 2, 4)
SWITCHING CHARACTERISTICS
Propagation Delay Time Low to High,
IN Rising (IN to OUT) (Notes 2, 4)
Propagation Delay Time High to Low,
IN Falling (IN to OUT) (Notes 2, 4)
Rise Time (Note 4)
Fall Time (Note 4)
Delay Matching between 2 Channels
(Note 5)
t
d1
t
d2
t
r
t
f
t
m
t
d3
t
d4
V
IN_H
V
IN_L
R
OH
R
OL
I
Source
I
Source
I
Sink
I
Sink
V
thH
V
thL
10
ms
Input rising from logic low
Input falling from logic high
OUTA = OUTB = Inverter Configuration
OUTA = OUTB = Buffer Configuration
1.8
0.8
2.0
1.0
200
200
2.2
1.2
V
V
kW
kW
IOUT = −10 mA
IOUT = +10 mA
OUTA/OUTB = GND
200 ns Pulse
OUTA/OUTB = 5.0 V
200 ns Pulse
OUTA/OUTB = VDD
200 ns Pulse
OUTA/OUTB = 5.0 V
200 ns Pulse
0.8
0.8
5
4.5
5
3.5
2
2
W
W
A
A
A
A
Low to High Transition
High to Low Transition
1.8
0.8
2.0
1.0
200
2.2
1.2
V
V
kW
C
Load
= 1.8 nF
C
Load
= 1.8 nF
16
16
20
20
29
29
ns
ns
C
Load
= 1.8 nF
C
Load
= 1.8 nF
C
Load
= 1.8 nF
C
Load
= 1.8 nF
INA = INB, OUTA and OUTB at 50%
Transition Point
16
16
20
20
8
8
1
29
29
15
15
4
ns
ns
ns
ns
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Guaranteed by design.
3. Not production tested, guaranteed by design and statistical analysis.
4. See timing diagrams in Figure 2, Figure 3, Figure 4 and Figure 5.
5. Guaranteed by characterization.
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