512MB, 1GB (x72, ECC, SR): 200-Pin DDR2 SDRAM VLP SORDIMM
Features
DDR2 SDRAM VLP SORDIMM
MT9HVF6472RH – 512MB
MT9HVF12872RH – 1GB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• 200-pin, very low-profile (ATCA compatible), small-
outline registered dual in-line memory module (VLP
SORDIMM)
• Fast data transfer rates: PC2-3200, PC2-4200,
PC2-5300, or PC2-6400
• 512MB (64 Meg x 72), 1GB (128 Meg x 72)
• Supports ECC error detection and correction
• Vdd = Vddq = +1.8V
• Vddspd = +3.0V to +3.6V
• JEDEC-standard 1.8V I/O (SSTL_18-compatible)
• Differential data strobe (DQS, DQS#) option
• 4n-bit prefetch architecture
• Multiple internal device banks for concurrent
operation
• Programmable CAS# latency (CL)
• Posted CAS additive latency (AL)
• WRITE latency = READ latency - 1
t
CK
• Programmable burst lengths: 4 or 8
• Adjustable data-output drive strength
• 64ms, 8192-cycle refresh
• On-die termination (ODT)
• Serial presence-detect (SPD) with EEPROM
• PLL to reduce system clock line loading
• Gold edge contacts
• Single rank
• I
2
C temperature sensor
Figure 1:
200-Pin VLP SORDIMM
(ATCA Compatible)
PCB height: 17.9mm (0.70in)
Options
• Operating temperature
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
• Package
–
200-pin DIMM (lead-free)
• Frequency/CAS latency
2
–
2.5ns @ CL = 5 (DDR2-800)
–
2.5ns @ CL = 6 (DDR2-800)
–
3.0ns @ CL = 5 (DDR2-667)
–
3.75ns @ CL = 4 (DDR2-533)
–
5.0ns @ CL = 3 (DDR2-400)
3
• PCB height
–
17.9mm (0.70in)
1
Marking
None
I
Y
-80E
-800
-667
-53E
-40E
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. CL = CAS (READ) latency; registered mode
will add one clock cycle to CL.
3. Not recommended for new designs.
Table 1:
Speed
Grade
-80E
-800
-667
-53E
-40E
Key Timing Parameters
Industry
Nomenclature
PC2-6400
PC2-6400
PC2-5300
PC2-4200
PC2-3200
Data Rate (MT/s)
CL = 6
–
800
–
–
–
CL = 5
800
667
667
–
–
CL = 4
533
533
533
533
400
CL = 3
–
–
400
400
400
t
RCD
t
RP
t
RC
(ns)
12.5
15
15
15
15
(ns)
12.5
15
15
15
15
(ns)
55
55
55
55
55
PDF: 09005aef82882ca3/Source: 09005aef82882c52
HVF9C64_128x72RH.fm - Rev. C 1/09 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512MB, 1GB (x72, ECC, SR): 200-Pin DDR2 SDRAM VLP SORDIMM
Features
Table 2:
Parameter
Refresh count
Row address
Device bank address
Device page size per bank
Device configuration
Column address
Module rank address
Addressing
512MB
8K
16K A[13:0]
4 BA[1:0]
1KB
512Mb (64 Meg x 8)
1K A[9:0]
1 (S0#)
1GB
8K
16K A[13:0]
8 BA[2:0]
1KB
1Gb (128 Meg x 8)
1K A[9:0]
1 (S0#)
Table 3:
Part Numbers and Timing Parameters – 512MB Modules
Base device: MT47H64M8, 512Mb DDR2 SDRAM
1
Module
Density
512MB
512MB
512MB
512MB
512MB
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL-
t
RCD-
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Part Number
2
MT9HVF6472RH(I)Y-80E__
MT9HVF6472RH(I)Y-800__
MT9HVF6472RH(I)Y-667__
MT9HVF6472RH(I)Y-53E__
MT9HVF6472RH(I)Y-40E__
Notes:
Configuration
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
64 Meg x 72
1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) designating component and PCB
revisions. Consult factory for current revision codes. Example: MT9HVF6472RHY-667F1.
Table 4:
Part Numbers and Timing Parameters – 1GB Modules
Base device: MT47H128M8, 1Gb DDR2 SDRAM
1
Module
Density
1GB
1GB
1GB
1GB
1GB
Module
Bandwidth
6.4 GB/s
6.4 GB/s
5.3 GB/s
4.3 GB/s
3.2 GB/s
Memory Clock/
Data Rate
2.5ns/800 MT/s
2.5ns/800 MT/s
3.0ns/667 MT/s
3.75ns/533 MT/s
5.0ns/400 MT/s
Latency
(CL-
t
RCD-
t
RP)
5-5-5
6-6-6
5-5-5
4-4-4
3-3-3
Part Number
2
MT9HVF12872RH(I)Y-80E__
MT9HVF12872RH(I)Y-800__
MT9HVF12872RH(I)Y-667__
MT9HVF12872RH(I)Y-53E__
MT9HVF12872RH(I)Y-40E__
Notes:
Configuration
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
128 Meg x 72
1. Data sheets for the base devices can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) designating component and PCB
revisions. Consult factory for current revision codes. Example: MT9HVF12872RHY-667E1.
PDF: 09005aef82882ca3/Source: 09005aef82882c52
HVF9C64_128x72RH.fm - Rev. C 1/09 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
512MB, 1GB (x72, ECC, SR): 200-Pin DDR2 SDRAM VLP SORDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 5:
Pin Assignments
200-Pin VLP SORDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
Vref
DQ0
Vss
DQ1
DQS0#
DQS0
Vss
DQ2
DQ3
Vss
DQ8
DQ9
Vss
DQS1#
DQS1
Vss
DQ10
DQ11
Vss
DQ16
DQ17
Vss
DQS2#
DQS2
Vss
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
DQ18
DQ19
Vss
DQ24
DQ25
Vss
DQS3#
DQS3
Vss
DQ26
DQ27
Vss
CB0
CB1
Vss
DQS8#
DQS8
Vss
CKE0
NC
EVENT#
Vdd
A12
A9
A7
Notes:
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
Vdd
A5
A3
A2
Vdd
A10
BA0
RAS#
Vdd
CAS#
NC
Vdd
NC
NC
DQ32
Vss
DQ33
DQS4#
DQS4
Vss
DQ34
DQ35
Vss
DQ40
DQ41
151
Vss
153 DQS5#
155 DQS5
157
Vss
159 DQ42
161 DQ43
163
Vss
165 DQ48
167 DQ49
169
Vss
171 DQS6#
173 DQS6
175
Vss
177 DQ50
179 DQ51
181
Vss
183 DQ56
185 DQ57
187
Vss
189 DQS7#
191 DQS7
193 DQ58
195
Vss
197 DQ59
199 Vddspd
200-Pin VLP SORDIMM Back
Pin Symbol Pin Symbol
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
Vss
DQ4
DQ5
Vss
DM0
Vss
DQ6
DQ7
Vss
DQ12
DQ13
Vss
DM1
Vss
DQ14
DQ15
Vss
DQ20
DQ21
Vss
RESET#
DM2
Vss
DQ22
DQ23
52
Vss
54
DQ28
56
DQ29
58
Vss
60
DM3
62
Vss
64
DQ30
66
DQ31
68
Vss
70
CB4
72
CB5
74
Vss
76
DM8
78
Vss
80
CB6
82
CB7
84
Vss
86
CB2
88
CB3
90
Vss
92
1
NF/BA2
94
NC
96
A11
98
Vdd
100
A8
Pin
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
Symbol Pin Symbol
A6
A4
Vdd
A1
A0
BA1
Vdd
WE#
S0#
ODT0
A13
Vdd
CK0
CK0#
Vss
DQ36
DQ37
Vss
DM4
Vss
DQ38
DQ39
Vss
DQ44
DQ45
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
Vss
DM5
Vss
DQ46
DQ47
Vss
DQ52
DQ53
Vss
DM6
Vss
DQ54
DQ55
Vss
DQ60
DQ61
Vss
DM7
DQ62
Vss
DQ63
SDA
SCL
SA1
SA0
1. Pin 92 is NF for 512MB, BA2 for 1GB.
PDF: 09005aef82882ca3/Source: 09005aef82882c52
HVF9C64_128x72RH.fm - Rev. C 1/09 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
512MB, 1GB (x72, ECC, SR): 200-Pin DDR2 SDRAM VLP SORDIMM
Pin Assignments and Descriptions
Table 6:
Symbol
A[13:0]
Pin Descriptions
Type
Input
Description
Address inputs:
Provide the row address for ACTIVE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank
selected by BA[2/1:0]) or all device banks (A10 HIGH). The address inputs also provide the
op-code during a LOAD MODE command.
Bank address inputs:
BA[2/1:0] define the device bank to which an ACTIVE, READ, WRITE,
or PRECHARGE command is being applied. BA[2/1:0] define which mode register (MR,
EMR1, EMR2, and EMR3) is loaded during the LOAD MODE command. BA[1:0] (512MB) and
BA[2:0] (1GB).
Clock:
CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data (DQ, DQS, and DQS#) is referenced to the crossings of CK and CK#.
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DDR2 SDRAM.
Input data mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of DQS. Although the DM pins are input-only, DM loading is designed to match
that of the DQ and DQS pins.
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR2 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will
be ignored if disabled via the LOAD MODE command.
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset:
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal
can be used during power-up to ensure that CKE is LOW and DQ are High-Z.
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Serial address inputs:
These pins are used to configure the SPD EEPROM address range on
the I
2
C bus.
Serial clock for SPD EEPROM:
SCL is used to synchronize communication to and from the
SPD EEPROM.
Check bits.
Data input/output:
Bidirectional data bus.
Data strobe:
DQS# is only used when differential data strobe mode is enabled via the
LOAD MODE command. Output with read data. Edge-aligned with read data. Input with
write data. Center-aligned with write data.
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out of
the SPD EEPROM on the module on the I
2
C bus.
Temperature event:
The EVENT# pin is asserted by the temperature sensor when critical
temperature thresholds have been exceeded.
Power supply:
1.8V ±0.1V.
SPD EEPROM power supply:
+1.7V to +3.6V.
Reference voltage:
Vdd/2.
Ground.
No connect:
These pins are not connected on the module.
No function:
Connected within the module, but provides no functionality.
BA[2:0]
Input
CK0, CK0#
Input
CKE0
DM[8:0]
Input
Input
ODT0
Input
RAS#, CAS#,
WE#
RESET#
S0#
SA[1:0]
SCL
CB[7:0]
DQ[63:0]
DQS[8:0],
DQS#[8:0]
SDA
EVENT#
Input
Input
Input
Input
Input
I/O
I/O
I/O
I/O
Output
(open
drain)
Supply
Supply
Supply
Supply
–
–
Vdd
Vddspd
Vref
Vss
NC
NF
PDF: 09005aef82882ca3/Source: 09005aef82882c52
HVF9C64_128x72RH.fm - Rev. C 1/09 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
512MB, 1GB (x72, ECC, SR): 200-Pin DDR2 SDRAM VLP SORDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2:
Functional Block Diagram
RS0#
DQS0#
DQS0
DM0
DM CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS4#
DQS4
DM4
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
U1
U6
DQS1#
DQS1
DM1
DM CS# DQS DQS#
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS5#
DQS5
DM5
DM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
U12
U9
DQS2#
DQS2
DM2
DM CS# DQS DQS#
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS6#
DQS6
DM6
DM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
U2
U7
DQS3#
DQS3
DM3
DM CS# DQS DQS#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS7#
DQS7
DM7
DM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CS# DQS DQS#
U11
U8
DQS8#
DQS8
DM8
DM CS# DQS DQS#
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U4
CK0
CK0#
PLL
RESET#
U10
U13
SPD EEPROM
WP A0
SCL
A1
A2
DDR2 SDRAM x 2
DDR2 SDRAM x 2
DDR2 SDRAM and register
DDR2 SDRAM x 2
DDR2 SDRAM x 2
SDA
Vss SA0 SA1 Vss
U3
Temp Sensor
SDA
U5
S0#
BA[2:0]
A[13:0]
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
EVT A0
RS0#: DDR2 SDRAM
RB[2:0]: DDR2 SDRAM
RA[13:0]: DDR2 SDRAM
RRAS#: DDR2 SDRAM
RCAS#: DDR2 SDRAM
RWE#: DDR2 SDRAM
RCKE0: DDR2 SDRAM
RODT0: DDR2 SDRAM
A1
A2
R
E
G
I
S
T
E
R
SA0 SA1 Vss
EVENT#
Vddspd
Vdd
Vref
Vss
SPD EEPROM, temperature sensor
DDR2 SDRAM
DDR2 SDRAM
DDR2 SDRAM
PDF: 09005aef82882ca3/Source: 09005aef82882c52
HVF9C64_128x72RH.fm - Rev. C 1/09 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2007 Micron Technology, Inc. All rights reserved.
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