ESD8004
ESD Protection Diode
Low Capacitance Array for High Speed
Data Lines
The ESD8004 is designed to protect high speed data lines from
ESD. Ultra−low capacitance and low ESD clamping voltage make this
device an ideal solution for protecting voltage sensitive high speed
data lines. The flow−through style package allows for easy PCB layout
and matched trace lengths necessary to maintain consistent impedance
between high speed differential lines such as USB 3.0/3.1.
Features
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MARKING
DIAGRAM
UDFN10
CASE 517BB
4DMG
G
•
Low Capacitance (0.35 pF Max, I/O to GND)
•
Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
•
Low ESD Clamping Voltage
•
SZ Prefix for Automotive and Other Applications Requiring Unique
Site and Control Change Requirements; AEC−Q101 Qualified and
PPAP Capable
•
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Typical Applications
4D
= Specific Device Code (tbd)
M
= Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONFIGURATION AND SCHEMATIC
N/C N/C
10
1
I/O
I/O
Pin 1
GND N/C N/C
8
3
GND
I/O
Pin 4
9
2
I/O
7
4
I/O
6
5
I/O
•
USB 3.0/3.1
•
eSATA
•
DisplayPort
I/O
Pin 2
I/O
Pin 5
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Operating Junction Temperature Range
Storage Temperature Range
Lead Solder Temperature
−
Maximum (10 Seconds)
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
Symbol
T
J
T
stg
T
L
ESD
ESD
Value
−55
to +125
−55
to +150
260
±15
±15
Unit
°C
°C
°C
kV
kV
=
Pins 3, 8
Note: Common GND
−
Only Minimum of 1 GND connection required
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
ORDERING INFORMATION
Device
ESD8004MUTAG
SZESD8004MUTAG
Package
UDFN10
(Pb−Free)
UDFN10
(Pb−Free)
Shipping
3000 / Tape &
Reel
3000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2015
November, 2017
−
Rev. 6
1
Publication Order Number:
ESD8004/D
ESD8004
See Application Note AND8308/D for further description of
survivability specs.
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
V
RWM
I
R
V
BR
I
T
V
HOLD
I
HOLD
R
DYN
I
PP
V
C
Parameter
Working Peak Voltage
Maximum Reverse Leakage Current @ V
RWM
Breakdown Voltage @ I
T
Test Current
Holding Reverse Voltage
Holding Reverse Current
Dynamic Resistance
Maximum Peak Pulse Current
Clamping Voltage @ I
PP
V
C
= V
HOLD
+ (I
PP
* R
DYN
)
R
DYN
−I
PP
V
BR
V
C
V
RWM
V
HOLD
I
R
I
T
I
HOLD
V
C
V
R
DYN
I
PP
I
V
C
= V
HOLD
+ (I
PP
* R
DYN
)
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Reverse Leakage Current
Holding Reverse Voltage
Holding Reverse Current
Clamping Voltage (Note 1)
Clamping Voltage
TLP (Note 2)
See Figures 5 through 8
Symbol
V
RWM
V
BR
I
R
V
HOLD
I
HOLD
V
C
V
C
I/O Pin to GND
I
T
= 1 mA, I/O Pin to GND
V
RWM
= 3.3 V, I/O Pin to GND
I/O Pin to GND
I/O Pin to GND
IEC61000−4−2,
±8
KV Contact
I
PP
= 8 A
I
PP
=
−8
A
I
PP
= 16 A
I
PP
=
−16
A
R
DYN
C
J
I/O Pin to GND
GND to I/O Pin
V
R
= 0 V, f = 1 MHz between I/O Pins and GND
V
R
= 0 V, f = 2.5 GHz between I/O Pins and GND
V
R
= 0 V, f = 1 MHz, between I/O Pins
IEC 61000−4−2 Level 2 equivalent
(±4 kV Contact,
±4
kV Air)
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact,
±15
kV Air)
1.19
25
See Figures 1 and 2
4.9
−4.5
8.0
−8.0
0.40
0.45
0.30
0.25
0.15
0.35
0.30
0.20
W
pF
5.5
7.0
1.0
Conditions
Min
Typ
Max
3.3
Unit
V
V
mA
V
mA
V
V
Dynamic Resistance
Junction Capacitance
(See Figures 9 & 10)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. For test procedure see Figures 3 and 4 and application note AND8307/D.
2. ANSI/ESD STM5.5.1
−
Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z
0
= 50
W,
t
p
= 100 ns, t
r
= 4 ns, averaging window; t
1
= 30 ns to t
2
= 60 ns.
90
80
70
60
VOLTAGE (V)
50
40
30
20
10
0
−10
−20
0
20
40
60
TIME (ns)
80
100
120
140
VOLTAGE (V)
10
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−20
0
20
40
60
TIME (ns)
80
100
120
140
Figure 1. IEC61000−4−2 +8 kV Contact ESD
Clamping Voltage
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2
Figure 2. IEC61000−4−2
−8
kV Contact
Clamping Voltage
ESD8004
IEC 61000−4−2 Spec.
Test Volt-
age (kV)
2
4
6
8
First Peak
Current
(A)
7.5
15
22.5
30
Current at
30 ns (A)
4
8
12
16
Current at
60 ns (A)
2
4
6
8
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
I @ 30 ns
IEC61000−4−2 Waveform
I
peak
100%
90%
Level
1
2
3
4
Figure 3. IEC61000−4−2 Spec
Device
ESD Gun
Under
Test
Oscilloscope
50
W
Cable
50
W
Figure 4. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8307/D
−
Characterization of ESD Clamping
Performance.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
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3
ESD8004
20
18
16
TLP CURRENT (A)
14
12
10
8
6
4
2
0
0
2
4
6
8
V
C
= V
HOLD
+ (I
PP
* R
DYN
)
8
6
4
2
10
−20
−18
EQUIVALENT V
IEC
(kV)
TLP CURRENT (A)
−14
−12
−10
−8
−6
−4
−2
0
20
0
0
2
4
6
8
10
12
14
16
18
0
20
2
4
6
EQUIVALENT V
IEC
(kV)
−16
8
10
10
12
14
16
18
V
C
, VOLTAGE (V)
V
C
, VOLTAGE (V)
Figure 5. Positive TLP I−V Curve
NOTE:
Figure 6. Negative TLP I−V Curve
TLP parameter: Z
0
= 50
W,
t
p
= 100 ns, t
r
= 300 ps, averaging window: t
1
= 30 ns to t
2
= 60 ns. V
IEC
is the equivalent voltage
stress level calculated at the secondary peak of the IEC 61000−4−2 waveform at t = 30 ns with 2 A/kV. See TLP description
below for more information.
Transmission Line Pulse (TLP) Measurement
Transmission Line Pulse (TLP) provides current versus
voltage (I−V) curves in which each data point is obtained
from a 100 ns long rectangular pulse from a charged
transmission line. A simplified schematic of a typical TLP
system is shown in Figure 7. TLP I−V curves of ESD
protection devices accurately demonstrate the product’s
ESD capability because the 10s of amps current levels and
under 100 ns time scale match those of an ESD event. This
is illustrated in Figure 8 where an 8 kV IEC 61000−4−2
current waveform is compared with TLP current pulses at
8 A and 16 A. A TLP I−V curve shows the voltage at which
the device turns on as well as how well the device clamps
voltage over a range of current levels. For more information
on TLP measurements and how to interpret them please
refer to AND9007/D.
L
50
W
Coax
Cable
S
Attenuator
÷
10 MW
I
M
50
W
Coax
Cable
V
M
V
C
Oscilloscope
DUT
Figure 7. Simplified Schematic of a Typical TLP
System
Figure 8. Comparison Between 8 kV IEC 61000−4−2 and 8 A and 16 A TLP Waveforms
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4
ESD8004
1.0
0.9
0.8
0.7
C
J
, (pF)
0.6
0.5
0.4
0.3
0.2
0.1
0
0
0.5
1
1.5
2
2.5
3
3.5
V
R
, VOLTAGE (V)
Figure 9. Junction Capacitance; V
R
= 3.5 V
−
0 V, f = 1 MHz, I/O
−
GND, dV/dt = 214 mV/s
Figure 10. Junction Capacitance; V
R
= 0 V,
f = 500 MHz
−
10 GHz
Without ESD8004
With ESD8004
Figure 11. USB 3.0 Eye Diagram with and without ESD8004. 5 Gb/s
Without ESD8004
With ESD8004
Figure 12. USB 3.1 Eye Diagram with and without ESD8004. 10 Gb/s
See application note AND9075/D for further description of eye diagram testing methodology.
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