NCP1850
Fully Integrated Li-Ion
Switching Battery Charger
with Power Path
Management and USB
On-The-Go Support
The NCP1850 is a fully programmable single cell Lithium−ion
switching battery charger optimized for charging from a USB
compliant input supply and AC adaptor power source. The device
integrates a synchronous PWM controller, power MOSFETs, and the
entire charge cycle monitoring including safety features under
software supervision. An optional battery FET can be placed between
the system and the battery in order to isolate and supply the system.
The NCP1850 junction temperature and battery temperature are
monitored during charge cycle, and both current and voltage can be
modified accordingly through I
2
C setting. The charger activity and
status are reported through a dedicated pin to the system. The input pin
is protected against overvoltages.
The NCP1850 also provides USB OTG support by boosting the
battery voltage as well as providing overvoltage protected power
supply for USB transceiver.
Features
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MARKING
DIAGRAM
1850
AYWW
G
WLCSP25
CASE 567FZ
1850
A
Y
WW
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 29 of this data sheet.
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1.5 A Buck Converter with Integrated Pass Devices
Input Current Limiting to Comply to USB Standard
Automatic Charge Current for AC Adaptor Charging
High Accuracy Voltage and Current Regulation
Input Overvoltage Protection up to +28 V
Factory Mode
250 mA Boosted Supply for USB OTG Peripherals
Reverse Leakage Protection Prevents Battery Discharge
Protected USB Transceiver Supply Switch
Dynamic Power Path with Optional Battery FET
Battery Temperature Sensing for Safe Operation
Silicon Temperature Supervision for Optimized Charge Cycle
Safety Timers
Flag Output for Charge Status and Interrupts
INTB Output for Interrupts
I
2
C Control Bus up to 3.4 MHz
Small Footprint 2.2 x 2.55 mm CSP Package
These Devices are Pb−Free and are RoHS Compliant
Smart Phone
Handheld Devices
Tablets
PDAs
Applications
©
Semiconductor Components Industries, LLC, 2013
May, 2013
−
Rev. 1
1
Publication Order Number:
NCP1850/D
NCP1850
PIN CONNECTIONS
1
A
IN
2
IN
3
SPM
4
SDA
5
SCL
B
CAP
CAP
OTG
ILIMB
FLAG
C
SW
SW
AGND
ILIM
NTC
D
PGND
PGND
SENSP
SENSN
FET
E
CBOOT
TRANS
CORE
WEAK
BAT
(Top View)
Figure 1. Package Outline CSP
Table 1. PIN FUNCTION DESCRIPTION
Pin
A1
A2
A3
A4
A5
B1
B2
B3
Name
IN
IN
SPM
SDA
SCL
CAP
CAP
OTG
Type
POWER
POWER
DIGITAL INPUT
DIGITAL
BIDIRECTIONAL
DIGITAL INPUT
POWER
POWER
DIGITAL INPUT
Description
Battery Charger Input. These two pins must be decoupled by at least 1
mF
capacitor and
connected together.
System Power Monitor input.
I
2
C data line
I
2
C clock line
CAP pin is the intermediate power supply input for all internal circuitry. Bypass with at
least 4.7
mF
capacitor. Must be tied together.
Enables OTG boost mode.
OTG = 0, the boost is powered OFF
OTG = 1 turns boost converter ON
Connect to interrupt pin of the system, active low
Charging state active low. This is an open drain pin that can either drive a status LED or
connect to interrupt pin of the system.
Connection from power MOSFET to the Inductor. These pins must be connected together.
B4
B5
C1
C2
C3
C4
C5
D1
D2
D3
ILIMB
FLAG
SW
SW
AGND
ILIM
NTC
PGND
PGND
SENSP
OPEN DRAIN
OUTPUT
OPEN DRAIN
OUTPUT
ANALOG OUTPUT
ANALOG OUTPUT
ANALOG GROUND
DIGITAL INPUT
ANALOG INPUT
POWER GND
POWER GND
ANALOG INPUT
Analog ground / reference. This pin should be connected to the ground plane and must be
connected together.
Input current limiter level selection (can be defeated by I
2
C).
Input for the battery NTC (10 KW / B = 3900) or (4.7 KW / B = 3900) If not used, this pin
must be tied to GND to configure the NCP1850 and warn that NTC is not used.
Power ground. These pins should be connected to the ground plane and must be
connected together.
Current sense input. This pin is the positive current sense input. It should be connected to
the R
SENSE
resistor positive terminal.
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NCP1850
Table 1. PIN FUNCTION DESCRIPTION
Pin
D4
Name
SENSN
Type
ANALOG INPUT
Description
Current sense input. This pin is the negative current sense input. It should be connected to
the R
SENSE
resistor negative terminal. This pin is also voltage sense input of the voltage
regulation loop when the FET is present and open.
Battery FET driver output. When not used, this pin must be directly tied to ground.
Floating Bootstrap connection. A 10 nF capacitor must be connected between CBOOT
and SW.
Output supply to USB transceiver. This pin can source a maximum of 30 mA to the
external USB PHY or any other IC that needs +5 V USB. This pin is Overvoltage protected
and will never be higher than 5.5 V. This pin should be bypassed by a 100 nF ceramic
capacitor.
5 V reference voltage of the IC. This pin should be bypassed by a 2.2
mF
capacitor. No
load must be connected to this pin.
Weak battery charging current source input.
Battery connection
D5
E1
E2
FET
CBOOT
TRANS
ANALOG OUTPUT
ANALOG IN/OUT
ANALOG OUTPUT
E3
E4
E5
CORE
WEAK
BAT
ANALOG OUTPUT
ANALOG OUTPUT
ANALOG INPUT
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NCP1850
Table 2. MAXIMUM RATINGS
Rating
IN (Note 1)
CAP (Note 1)
Power balls: SW, CBOOT (Note 1)
IN pin with respect to VCAP
SW with respect to SW
Sense/Control balls: SENSP, SENSN, VBAT, FET, TRANS, CORE, NTC, FLAG,
INTB and WEAK. (Note 1)
Digital Input: SCL, SDA, SPM, OTG, ILIM (Note 1)
Input Voltage
Input Current
Human Body Model (HBM) ESD Rating are (Note 2)
Machine Model (MM) ESD Rating are (Note 2)
Latch up Current (Note 3):
All Digital pins( V
DG
), FET
All others pins.
Storage Temperature Range
Maximum Junction Temperature (Note 4)
Moisture Sensitivity (Note 5)
Symbol
V
IN
V
CAP
V
PWR
V
IN_CAP
V
SW_CAP
V
CTRL
Value
−0.3
to +28
−0.3
to +28
−0.3
to +24
−0.3
to +7.0
−0.3
to +7.0
−0.3
to +7.0
Unit
V
V
V
V
V
V
V
DG
I
DG
ESD HBM
ESD MM
I
LU
−0.3
to +7.0 V
20
2000
200
10
±100
−65
to + 150
−40
to + TSD
Level 1
V
mA
V
V
mA
T
STG
T
J
MSL
°C
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. With respect to PGND. According to JEDEC standard JESD22−A108
2. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM)
±2.0
kV per JEDEC standard: JESD22−A114 for all pins.
Machine Model (MM)
±200
V per JEDEC standard: JESD22−A115 for all pins.
3. Latch up Current Maximum Rating:
±100
mA or per
±10
mA JEDEC standard: JESD78 class II.
4. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation. See Electrical Characteristics.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020.
Table 3. OPERATING CONDITIONS
Symbol
V
IN
V
DG
T
A
I
SINK
C
IN
C
CAP
C
CORE
C
OUT
L
X
R
SNS
R
qJA
T
J
Parameter
Operational Power Supply (Note 6)
Digital input voltage level
Ambient Temperature Range
FLAG sink current
Decoupling input capacitor
Decoupling Switcher capacitor
Decoupling core supply capacitor
Decoupling system capacitor
Switcher Inductor
Current sense resistor
Thermal Resistance Junction−to−Air
Junction Temperature Range
(Notes 7 and 8)
−40
1
4.7
2.2
10
2.2
68
60
25
+125
Conditions
Min
3
0
−40
25
Typ
Max
V
INOV
5.5
+85
10
Unit
V
V
°C
mA
mF
mF
mF
mF
mH
mW
°C/W
°C
6. OVLO is selectable per metal option (see ELECTRICAL CHARACTERISTICS table).
7. A thermal shutdown protection avoids irreversible damage on the device due to power dissipation. See Electrical Characteristics.
8. The R
qJA
is dependent on the PCB heat dissipation. Board used to drive this data was a 2s2p JEDEC PCB standard.
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NCP1850
Table 4. ELECTRICAL CHARACTERISTICS
Min & Max Limits apply for T
A
between
−40°C
to +85°C and T
J
up to + 125°C for V
IN
between 3.6 V to 7 V (Unless otherwise noted).
Typical values are referenced to T
A
= + 25°C and V
IN
= 5 V (Unless otherwise noted).
Symbol
INPUT VOLTAGE
V
INDET
V
BUSUV
V
BUSOV
V
INOV
V
INOV
Valid input detection threshold
V
IN
rising
V
IN
falling
USB under voltage detection
V
IN
falling
Hysteresis
USB over voltage detection
V
IN
rising
Hysteresis
Valid input high threshold
V
IN
rising
Hysteresis
3.55
2.95
4.3
50
5.55
25
7.1
200
3.6
3.0
4.4
100
5.65
75
7.2
300
3.65
3.05
4.5
150
5.75
125
7.3
400
V
V
V
mV
V
mV
V
mV
Parameter
Conditions
Min
Typ
Max
Unit
INPUT CURRENT LIMITING
I
INLIM
Input current limit
V
IN
= 5 V
I
INLIM
set to
100 mA
I
INLIM
set to
500 mA
I
INLIM
set to
900 mA
I
INLIM
set to
1500 mA
INPUT SUPPLY CURRENT
I
Q_SW
I
OFF
CHARGER DETECTION
V
CHGDET
Charger detection threshold
voltage
V
IN
– V
SENSN
, V
IN
rising
V
IN
– V
SENSN
, V
IN
falling
Battery leakage, V
BAT
= 4.2 V V
IN
= 0 V,
SDA = SCL = 0 V
Charger active state, Measured between
IN and CAP,V
IN
= 5 V
Programmable by I
2
C
Default value
Voltage regulation accuracy
Constant voltage mode, T
A
= 25°C
−0.5
−1
I2C Programmable granularity
BATTERY VOLTAGE THRESHOLD
V
SAFE
V
PRE
Safe charge threshold voltage
Conditioning charge threshold
voltage
V
BAT
rising
VFET = 3.1 V and 3.2 V
VFET = 3.3 V, 3.4 V, 3.5 V and 3.6 V
2.1
2.95
3.15
2.15
3
3.2
2.2
3.05
3.25
V
V
25
−
50
10
200
50
mV
VBUS supply current
No load, Charger active state
Charger not active, NTC disable
15
500
mA
mA
70
425
800
1.4
85
460
850
1.45
100
500
900
1.5
mA
mA
mA
A
REVERVE BLOCKING CURRENT
I
LEAK
R
RBFET
V
BAT
leakage current
Input RBFET On resistance
(Q1)
5
45
7
90
mA
mW
BATTERY AND SYSTEM VOLTAGE REGULATION
V
CHG
Output voltage range
3.3
3.6
0.5
1
mV
%
4.5
V
9. Minimum transition time from states to states.
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