NCV7349
High Speed Low Power CAN
Transceiver
Description
The NCV7349 CAN transceiver is the interface between
a controller area network (CAN) protocol controller and the physical
bus. The transceiver provides differential transmit capability to the bus
and differential receive capability to the CAN controller.
The NCV7349 is a new addition to the CAN high−speed transceiver
family complementing NCV734x CAN family and previous generations
of CAN transceivers such as AMIS42665, AMIS3066x, etc.
Due to the wide common−mode voltage range of the receiver inputs
and other design features, the NCV7349 is able to reach outstanding
levels of electromagnetic susceptibility (EMS). Similarly, very low
electromagnetic emission (EME) is achieved by the excellent
matching of the output signals.
Features
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MARKING
DIAGRAM
8
8
1
SOIC−8
CASE 751AZ
NV7349−x
ALYW
G
G
1
•
Compatible with the ISO 11898−5 Standard
•
High Speed (up to 1 Mbps)
•
V
IO
Pin on NCV7349−3 Version Allowing Direct Interfacing with
•
•
•
•
•
•
•
•
•
•
•
3 V to 5 V Microcontrollers
Very Low Current Standby Mode with Wake−up via the Bus
Low Electromagnetic Emission (EME) and Extremely High
Electromagnetic Immunity
Very Low EME without Common−mode (CM) Choke
No Disturbance of the Bus Lines with an Un−powered Node
Transmit Data (TxD) Dominant Time−out Function
Under All Supply Conditions the Chip Behaves Predictably
Very High ESD Robustness of Bus Pins, >10 kV System ESD Pulses
Thermal Protection
Bus Pins Short Circuit Proof to Supply Voltage and Ground
Bus Pins Protected Against Transients in an Automotive
These are Pb−Free Devices
NV7349−x = Specific Device Code
x = 0 or 3
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
1
TxD
2
GND
3
V
CC
4
RxD
NCV7349D10R2G
(Top View)
1
TxD
2
GND
3
V
CC
4
RxD
NCV7349D13R2G
(Top View)
7
CANH
6
CANL
5
V
IO
NV7349−3
ALYWG
G
8
STB
7
CANH
6
CANL
5
NC
NV7349−0
ALYWG
G
8
STB
Quality
•
NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
Typical Applications
•
Automotive
•
Industrial Networks
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
December, 2014 − Rev. 1
Publication Order Number:
NCV7349/D
NCV7349
Table 1. KEY TECHNICAL CHARACTERISTICS AND OPERATING RANGES
Symbol
V
CC
V
UV
V
CANH
V
CANL
V
CANH,Lmax
V
ESD
V
O(dif)(bus_dom)
CM−range
C
load
t
pd0
t
pd3
T
J
Parameter
Power supply voltage
Undervoltage detection voltage on pin Vcc
DC voltage at pin CANH
DC voltage at pin CANL
DC voltage at pin CANH and CANL during load
dump condition
Electrostatic discharge voltage
Differential bus output voltage in dominant state
Input common−mode range for comparator
Load capacitance on IC outputs
Propagation delay (NCV7349−0 version)
Propagation delay (NCV7349−3 version)
Junction temperature
See Figure 7
See Figure 7
0 < V
CC
< 5.5 V; no time limit
0 < V
CC
< 5.5 V; no time limit
0 < V
CC
< 5.5 V, less than one second
IEC 61000−4−2 at pins CANH and CANL
45
W
< R
LT
< 65
W
Guaranteed differential receiver thresh-
old and leakage current
(Note 1)
Conditions
Min
4.75
(4.5)
2
−50
−50
−
−15
1.5
−35
−
−
−
−40
Max
5.25
(5.5)
4
+50
+50
+58
15
3
+35
15
245
250
150
Unit
V
V
V
V
V
kV
V
V
pF
ns
ns
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. In the range of 4.5 V to 4.75 V and from 5.25 V to 5.5 V the chip is fully functional; some parameters may be outside of the specification.
BLOCK DIAGRAM
V
IO
(*)
5
V
IO
NCV7349
V
CC
3
Thermal
shutdown
TxD
1
Timer
V
IO
7
CANH
STB
8
Mode &
Wake−up
control
Driver control
6
CANL
RxD
4
Wake−up
Filter
COMP
GND
2
COMP
*On NCV7349−0 version pin 5 is not connected. V
IO
supply is provided by V
CC
.
Figure 1. Block Diagram
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NCV7349
TYPICAL APPLICATION
VBAT
IN
5 V − reg
OUT
V
CC
STB
Micro−
controller
TxD
RxD
NC
5
8
1
4
2
GND
GND
NCV7349−0
3
7
V
CC
R
LT
= 60
W
CANH
CAN
BUS
6
CANL
R
LT
= 60
W
Figure 2. Application Diagram, NCV7349−0
VBAT
IN
5 V − reg
OUT
IN
OUT
3 V − reg
V
IO
5
STB
Micro−
controller
TxD
RxD
8
1
4
NCV7349−3
6
2
GND
GND
3
7
V
CC
R
LT
= 60
W
CANH
CAN
BUS
CANL
R
LT
= 60
W
Figure 3. Application Diagram, NCV7349−3
Table 2. PIN FUNCTION DESCRIPTION
Pin
1
2
3
4
5
5
6
7
8
Name
TxD
GND
V
CC
RxD
NC
V
IO
CANL
CANH
STB
Description
Transmit data input; low input
Ù
Driving dominant on bus; internal pull−up current
Ground
Supply voltage
Receive data output; bus in dominant
Ù
low output
Not connected. On NCV7349−0 only.
Input / Output pins supply voltage. On NCV7349−3 only
Low−level CAN bus line (low in dominant mode)
High−level CAN bus line (high in dominant mode)
Standby mode control input; internal pull−up current
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NCV7349
FUNCTIONAL DESCRIPTION
NCV7349
has two versions which differ from each other
only by function of pin 5.
NCV7349−0:
Pin 5 is not connected. (see Figure 2)
NCV7349−3:
Pin 5 is V
IO
pin, which is supply pin for
transceiver digital inputs/output (supplying pins TxD, RxD,
STB) The V
IO
pin should be connected to microcontroller
supply pin. By using V
IO
supply pin shared with
microcontroller the I/O levels between microcontroller and
transceiver are properly adjusted. This adjustment allows in
applications with microcontroller supply down to 3 V to
easy communicate with the transceiver. (See Figure 3)
Operating Modes
Standby Mode
In standby mode both the transmitter and receiver are
disabled and a very low−power differential receiver
monitors the bus lines for CAN bus activity. The bus lines
are terminated to ground and supply current is reduced to a
minimum, typically 10
mA.
When a wake−up request is
detected by the low−power differential receiver, the signal
is first filtered and then verified as a valid wake signal after
a time period of t
wake
, the RxD pin is driven low by the
transceiver to inform the controller of the wake−up request.
V
IO
Supply pin
NCV7349 provides two modes of operation as illustrated
in Table 3. These modes are selectable through pin STB.
Table 3. OPERATING MODES
Pin
STB
Low
High
Pin RxD
Mode
Normal
Standby
Low
Bus dominant
Wake−up request
detected
High
Bus recessive
No wake−up
request detected
The V
IO
pin available only on NCV7349−3 version
should be connected to microcontroller supply pin. By using
V
IO
supply pin shared with microcontroller the I/O levels
between microcontroller and transceiver are properly
adjusted. See Figure 3. Pin V
IO
on NCV7349−3 does not
provide the internal supply voltage for low−power
differential receiver of the transceiver. Detection of
wake−up request is not possible when there is no supply
voltage on pin V
CC
.
Wake−up
Normal Mode
In the normal mode, the transceiver is able to
communicate via the bus lines. The signals are transmitted
and received to the CAN controller via the pins TxD and
RxD. The slopes on the bus lines outputs are optimized to
give low EME.
When a valid wake−up (dominant state longer than t
wake
)
is received during the standby mode the RxD pin is driven
low. The wake−up detection is not latched: RxD returns to
High state after t
dwakedr
when the bus signal is released back
to recessive – see Figure 4.
>t
Wake
CANH
CANL
<t
Wake
STB
RxD1
t
dwakerd
t
dwakedr
t
Wake(RxD)
normal
standby
time
Figure 4. NCV7349 Wake−up Behavior
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NCV7349
Over−temperature Detection
Fail Safe Features
A thermal protection circuit protects the IC from damage
by switching off the transmitter if the junction temperature
exceeds a value of approximately 170°C. Because the
transmitter dissipates most of the power, the power
dissipation and temperature of the IC is reduced. All other
IC functions continue to operate. The transmitter off−state
resets when the temperature decreases below the shutdown
threshold and pin TxD goes high. The thermal protection
circuit is particularly needed when a bus line short circuits.
TxD Dominant Time−out Function
A TxD dominant time−out timer circuit prevents the bus
lines being driven to a permanent dominant state (blocking
all network communication) if pin TxD is forced
permanently low by a hardware and/or software application
failure. The timer is triggered by a negative edge on pin TxD.
If the duration of the low−level on pin TxD exceeds the
internal timer value t
dom(TxD)
, the transmitter is disabled,
driving the bus into a recessive state. The timer is reset by a
positive edge on pin TxD.
This TxD dominant time−out time (t
dom(TxD)
) defines the
minimum possible bit rate to 15 kbps.
A current−limiting circuit protects the transmitter output
stage from damage caused by accidental short circuit to
either positive or negative supply voltage, although power
dissipation increases during this fault condition.
Undervoltage on V
CC
pin prevents the chip sending data
on the bus when there is not enough V
CC
supply voltage.
After supply is recovered TxD pin must be first released to
high to allow sending dominant bits again. Recovery time
from undervoltage detection is equal to t
d(stb−nm)
time.
V
IO
supply dropping below V
UVDVIO
undervoltage
detection level will cause the transmitter to disengage from
the bus (no bus loading) until the V
IO
voltage recovers
(NCV7349−3 version only).
The pins CANH and CANL are protected from
automotive electrical transients (according to ISO 7637; see
Figure 7). Pins TxD and STB are pulled high internally
should the input become disconnected. Pins TxD, STB and
RxD will be floating, preventing reverse supply should the
V
IO
supply be removed.
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FPGA/CPLD
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