June 2007
HYB18T512161B2F–20/25
512-Mbit x16 DDR2 SDRAM
DDR2 SDRAM
RoHS compliant
Internet Data Sheet
Rev. 1.1
Date: 2008-02-26
Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512161B2F–20/25
Revision History:
2007-06,
Rev. 1.1
Page
All
Subjects (major changes since last revision)
Typo Changes
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
05152007-ZYAH-ACMZ
2
Date: 2008-02-26
Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family for graphics application and
describes its main characteristics.
1.1
Features
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
• Data masks (DM) for write data
• 1.8 V
±
0.1V V
DD
for [–20/–25]
• 1.8 V
±
0.1V V
DDQ
for [–20/–25]
• Posted CAS by programmable additive latency for better
• DRAM organizations with 16 data in/outputs
command and data bus efficiency
• Double Data Rate architecture:
• Off-Chip-Driver impedance adjustment (OCD) and On-
– two data transfers per clock cycle
Die-Termination (ODT) for better signal quality.
– four internal banks for concurrent operation
• Auto-Precharge operation for read and write bursts
• Programmable CAS Latency: 3, 4, 5, 6, 7
• Auto-Refresh, Self-Refresh and power saving Power-
• Programmable Burst Length: 4 and 8
Down modes
• Average Refresh Period 7.8
μs
at a
T
CASE
lower than 85
• Differential clock inputs (CK and CK)
• Bi-directional, differential data strobes (DQS and DQS) are
°C, 3.9
μs
between 85 °C and 95 °C
transmitted / received with data. Edge aligned with read
• Full Strength and reduced Strength (60%) Data-Output
Drivers
data and center-aligned with write data.
• DLL aligns DQ and DQS transitions with clock
• 2kB page size
• Packages: P-TFBGA-84
• DQS can be disabled for single-ended data strobe
operation
• RoHS Compliant Products
1)
• Commands entered on each positive clock edge, data and
data mask are referenced to both edges of DQS
TABLE 1
Ordering Information for RoHS compliant products
Product Number
HYB18T512161B2F–20/25
Org.
×16
Clock (MHz)
500/400
Package
P-TFBGA-84
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
3
Date: 2008-02-26
Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
1.2
Description
All of the control and address inputs are synchronized with a
pair of externally supplied differential clocks. Inputs are
latched at the cross point of differential clocks (CK rising and
CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous
fashion.
A 15-bit address bus is used to convey row, column and bank
address information in a RAS-CAS multiplexing style.
An Auto-Refresh and Self-Refresh mode is provided along
with various power-saving power-down modes.
The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM is available in P-TFBGA package.
The 512-Mb DDR2 DRAM is a high-speed Double-Data-
Rate-Two CMOS DRAM device containing 536,870,912 bits
and internally configured as a quad-bank DRAM. The 512-Mb
device is organized as 8 Mbit
×
16 I/O
×
4 banks chip. These
devices achieve high speed transfer rates starting at
800 Mb/sec/pin for general applications.
The device is designed to comply with all DDR2 DRAM key
features:
1. posted CAS with additive latency,
2. write latency = read latency - 1,
3. normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
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Date: 2008-02-26
Internet Data Sheet
HYB18T512161B2F–20/25
512-Mbit Double-Data-Rate-Two SDRAM
2
2.1
Configuration
Chip Configuration
The chip configuration of a DDR2 SDRAM is listed by function in
Table 2.
The abbreviations used in the Ball# and Buffer Type
columns are explained in
Table 3
and
Table 4
respectively. The ball numbering for the FBGA package is depicted in
Figure 1.
TABLE 2
Chip Configuration of DDR2 SDRAM
Ball#
Clock Signals
J8
K8
CK
CK
I
I
SSTL
SSTL
Clock Signal CK, Complementary Clock Signal CK
Note: CK and CK are differential system clock inputs. All address
and control inputs are sampled on the crossing of the
positive edge of CK and negative edge of CK. Output (read)
data is referenced to the crossing of CK and CK (both
direction of crossing)
Clock Enable
Note: CKE HIGH activates and CKE LOW deactivates internal
clock signals and device input buffers and output drivers.
Taking CKE LOW provides Precharge Power-Down and
Self-Refresh operation (all banks idle), or Active Power-
Down (row Active in any bank). CKE is synchronous for
power down entry and exit and for self-refresh entry. Input
buffers excluding CKE are disabled during self-refresh.
CKE is used asynchronously to detect self-refresh exit
condition. Self-refresh termination itself is synchronous.
After
V
REF
has become stable during power-on and
initialisation sequence, it must be maintained for proper
operation of the CKE receiver. For proper self-refresh entry
and exit,
V
REF
must be maintained to this input. CKE must
be maintained HIGH throughout read and write accesses.
Input buffers, excluding CK, CK, ODT and CKE are
disabled during power-down
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Chip Select
Name
Ball
Type
Buffer
Type
Function
K2
CKE
I
SSTL
Control Signals
K7
L7
K3
L8
Address Signals
RAS
CAS
WE
CS
I
I
I
I
SSTL
SSTL
SSTL
SSTL
Rev. 1.1, 2007-06
05152007-ZYAH-ACMZ
5
Date: 2008-02-26
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