IDT5V9882T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
3.3V EEPROM
PROGRAMMABLE CLOCK
GENERATOR
FEATURES:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Three internal PLLs
Internal non-volatile EEPROM
FAST mode I
2
C serial interfaces
Input Frequency Ranges: 1MHz to 400MHz
Output Frequency Ranges: 4.9kHz to 500MHz
Reference Crystal Input with programmable oscillator gain and
programmable linear load capacitance
−
Crystal Frequency Range: 8MHz to 50MHz
Each PLL has an 8-bit pre-scaler and a 12-bit feedback-divider
10-bit post-divider blocks
Fractional Dividers
Two of the PLLs support Spread Spectrum Generation
capability
I/O Standards:
−
Outputs - 3.3V LVTTL/ LVCMOS, LVPECL, and LVDS
−
Inputs - 3.3V LVTTL/ LVCMOS
Programmable Slew Rate Control
Programmable Loop Bandwidth Settings
Programmable output inversion to reduce bimodal jitter
Individual output enable/disable
Power-down mode
3.3V V
DD
Available in TSSOP package
IDT5V9882T
DESCRIPTION:
The IDT5V9882T is a programmable clock generator intended for high
performance data-communications, telecommunications, consumer, and
networking applications. There are three internal PLLs, each individually
programmable, allowing for three unique non-integer-related frequencies.
The frequencies are generated from a single reference clock. The
reference clock can come from one of the two redundant clock inputs. A
glitchless automatic or manual switchover function allows any one of the
redundant clocks to be selected during normal operation.
The IDT5V9882T can be programmed through the use of the I
2
C
interfaces. The programming interface enables the device to be pro-
grammed when it is in normal operation or what is commonly known as in-
system programmable. An internal EEPROM allows the user to save and
restore the configuration of the device without having to reprogram it on
power-up.
Each of the three PLLs has an 8-bit pre-scaler and a 12-bit feedback
divider. This allows the user to generate three unique non-integer-related
frequencies. The PLL loop bandwidth is programmable to allow the user
to tailor the PLL response to the application. For instance, the user can tune
the PLL parameters to minimize jitter generation or to maximize jitter
attenuation. Spread spectrum generation and fractional divides are
allowed on two of the PLLs.
There are 10-bit post dividers on five of the six output banks. Two of the
six output banks are configurable to be LVTTL, LVPECL, or LVDS. The
other four output banks are LVTTL. The outputs are connected to the PLLs
via the switch matrix. The switch matrix allows the user to route the PLL
outputs to any output bank. This feature can be used to simplify and optimize
the board layout. In addition, each output's slew rate and enable/disable
function can be programmed.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
c
2010
Integrated Device Technology, Inc.
JUNE 2010
DSC 7064/2
IDT5V9882T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
XTALOUT
OSC.
XTALIN/REFIN
OUT1
P2 Divider
10-Bit
/2
OUT2
PLL 0
(1)
P4 Divider
OUT3
/2
(1)
PLL 1
10-Bit
OUT3
PLL 2
P6 Divider
10-Bit
/2
OUT4
EEPROM
Control Block for
Multi-Purpose I/O, Programming, Features
I
2
C_MFC
NOTE:
1. OUT3 pair can be configured to be LVDS, LVPECL, or two single-ended LVTTL outputs.
SHUTDOWN/OE/
SUSPEND
GIN0/SDAT
GIN1/SCLK/TCLK
2
IDT5V9882T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OUT2
V
DD
XTALIN/REFIN
XTALOUT
OUT1
GND
OUT3
OUT3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SHUTDOWN/OE/
SUSPEND
V
DD
I C_MFC
GIN1/SCLK
GIN0/SDAT
GND
OUT4
V
DD
2
TSSOP
TOP VIEW
PIN DESCRIPTION
Pin Name
XTALIN/REFIN
XTALOUT
GIN0/SDAT
GIN1/SCLK
SHUTDOWN/OE/SUSPEND
I2C_MFC
OUT1
OUT2
OUT3
OUT3
OUT4
V
DD
GND
Pin#
3
4
16
17
20
18
5
1
7
8
13
2, 13, 19
6, 15
I/O
I
O
I
I
I
I
O
O
O
O
O
Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
3-level
(1)
LVTTL
LVTTL
Adjustable
(2)
Adjustable
(2)
LVTTL
Description
CRYSTAL_IN - Reference crystal input or external reference clock input
CRYSTAL_OUT -Reference crystal feedback
Multi-purpose inputs. Can be used for Frequency Control or SDAT(I
2
C).
Multi-Purpose inputs. Can be used for Frequency Control or SDAT(I
2
C).
Enables/disables the outputs, PLLs or powers down the chip.
I
2
C (HIGH) or MFC Mode (MID)
Configurable clock output 1. Can also be used to buffer the reference clock.
Configurable clock output 2
Configurable clock output 3, Single-Ended or Differential when combined with
OUT3
Configurable complementary clock output 3, Single-Ended or Differential when combined with OUT3
Configurable clock output 4
3.3V Power Supply
Ground
NOTES:
1. 3-level inputs are static inputs and must be tied to V
DD
or GND or left floating. These inputs are internally biased to V
DD
/2. They are not hot-insertable or over voltage tolerant.
2. Outputs are user programmable to drive single-ended 3.3V LVTTL, differential LVDS, or differential LVPECL interface levels.
3
IDT5V9882T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
PLL FEATURES AND DESCRIPTIONS
D0 Divider
/ 8-bit
VCO
M0 Multiplier
/ 12-bit
Spread
Spectrum
Modulation
PLL0 Block Diagram
D1 Divider
/ 8-bit
VCO
M1 Multiplier
/ 12-bit
Spread
Spectrum
Modulation
PLL1 Block Diagram
D2 Divider
/ 8-bit
VCO
M2 Multiplier
/ 12-bit
PLL2 Block Diagram
4
IDT5V9882T
3.3V EEPROM PROGRAMMABLE CLOCK GENERATOR
INDUSTRIAL TEMPERATURE RANGE
Pre-Divider (D) Values
PLL0
PLL1
PLL2
1 - 255
1 - 255
1 - 255
Multiplier (M) Values
2 - 8190
2 - 8190
1 - 4095
Programmable Loop Bandwidth
yes
yes
yes
Spread Spectrum
Generation Capability
yes
yes
no
CRYSTAL INPUT (XTALIN/REFIN)
The crystal oscillators should be fundamental mode quartz crystals: overtone
crystals are not suitable. Crystal frequency should be specified for parallel
resonance with 50Ωmaximum equivalent series resonance.
When the XTALIN/REFIN pin is driven by a crystal, it is important to set the
internal oscillator inverter drive strength and internal tuning/load capacitor
values correctly to achieve the best clock performance. These values are
programmable through an I
2
C_MFC interface to allow for maximum compatibility
with crystals from various manufacturers, processes, performances, and
qualities. The internal load capacitors are true parallel-plate capacitors for ultra-
linear performance. Parallel-plate capacitors were chosen to reduce the
frequency shift that occurs when non-linear load capacitance interacts with load,
bias, supply, and temperature changes. External non-linear crystal load
capacitors should not be used for applications that are sensitive to absolute
frequency requirements. The value of the internal load capacitors are determined
by XTALCAP[7:0] bits, (0x07). The load capacitance can be set with a resolution
of 0.125 pF for a total crystal load range of 3.5pF to 35.4pF. Check with the
vendor's crystal load capacitance specification for the exact setting to tune the
internal load capacitor. The following equation governs how the total internal
load capacitance is set.
XTAL load cap = 3.5pF + XTALCAP[7:0] * 0.125pF (Eq. 1)
Parameter
XTALCAP
Bits
8
Step
0.125
Min
0
Max
32
Units
pF
Where F
IN
is the reference frequency, M is the total feedback-divider value,
D is the pre-scaler value, P is the total post-divider value, and F
OUT
is the resulting
output bank frequency. The value 2 in the denominator is due to the divide-
by-2 on each of the output banks OUT2-4. Note that OUT1 does not have any
type of post-divider. Also, programming any of the dividers may cause glitches
on the outputs.
Pre-Scaler
D[7:0] are the bits used to program the pre-scaler for each PLL, D0 for
PLL0, D1 for PLL1, and D2 for PLL2. The pre-scalers divide down the
reference clock with integer values ranging from 1 to 255. To maintain low jitter,
the divided down clock must be higher than 400KHz; it is best to use the smallest
D divider value possible. If D is set to '0x00', then this will power down the PLL
and all the outputs associated with that PLL.
When using an external reference clock instead of a crystal on the XTAL/
REFIN pin, the input load capacitors may be completely bypassed. This allows
for the input frequency to be up to 200MHz. When using an external reference
clock, the XTALOUT pin must be left floating, XTALCAP must be programmed
to the default value of "0", and crystal drive strength bit, XDRV (0x06), must
be set to the default value of "11".
PRE-SCALER, FEEDBACK-DIVIDER, AND
POST-DIVIDER
Each PLL incorporates an 8-bit pre-scaler and a 12-bit feedback divider
which allows the user to generate three unique non-integer-related frequencies.
For output banks OUT2-OUT4, each bank has a 10-bit post-divider. The
following equation governs how the frequency on output banks OUT2-4 is
calculated.
M
F
OUT
= F
IN
* D
( )
P*2
(Eq. 2)
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
