Hardware Design Guide, Revision 6
April 5, 2005
TMXF33625
Hypermapper™
622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0
1 Introduction
The last issue of this data sheet was July 12, 2004 - Revision 5. A change history is included in
Section 13 on page 82.
Red
change bars have been installed on all text, figures, and tables that were added or changed. All changes to the text are
highlighted in red. Changes within figures, and the figure title itself, are highlighted in red, if feasible. Formatting or
grammatical changes have not been highlighted. Deleted sections, paragraphs, figures, or tables will be specifically
mentioned.
The documentation package for the TMXF33625
Hypermapper
622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0 system
chip consists of the following documents:
The Register Description and the
Hypermapper
Family System Design Guide. These documents are available on a pass-
word-protected website.
The
Hypermapper
Product Description and the
Hypermapper
Hardware Design Guide (this document). These docu-
ments are available on the public website shown below.
http://www.agere.com/enterprise_metro_access/index.html
This document describes the hardware interfaces of the Agere Systems TMXF33625
Hypermapper
device. Information rel-
evant to the use of the device in a board design is covered. Pin descriptions, dc electrical characteristics, timing diagrams,
ac timing parameters, packaging, and operating conditions are covered. To contact Agere Systems, see the last page of
this document or contact your Agere representative.
622/155 Mbits/s SONET/SDH
ADM Front End
LOPOH
Clock & Data
24
622/155Mb/s
High-Speed IF
DS3/E3/DS1/E1/DS0 PDH
Tributary Termination
LOPOH
FRM (x12)
x28/x21
DS1/J1/E1
A
B
C
D
CHI/PSB
Rx/Tx Clocks/Syncs
5
W
P
8
8
CDR
CDR
TMUX-A
STSPP
A
STS
XC
A
From/To
TMUX A,B,C,D
SPEMPR x12
(3-5)
TPGM
(x4)
A
C
B
D
Clock/Sync 6
CG
8
FRM PLL IF
Clock & Data
A
CDR
CDR
TMUX-B
STSPP
B
STS
XC
B
B
D
W
P
8
8
C
MRXC
VTMPR (x12)
x28/x21
System
Interfaces
168
A
B
C
Clock/Sync 6
SPEMPR x12
(0-2)
(x24) DS3/E3
(x12) STS-1
96
A
C
B
D
Clock & Data
A
CDR
CDR
TMUX-C
STSPP
C
STS
XC
C
B
D
3
W
P
8
8
C
D
DS1/J1/E1
VT/TU
DS3/E3
144
(x12) NSMI
(x12) STS-1
(Total of 3 STS-1
max/partition)
Clock/Sync 6
STS1LT x12
E13 MUX
(x12)
A
C
B
D
M13 MUX
(x12)
A
C
B
D
1
3
1
CHI/PSB
Clock & Data
W
P
8
8
A
CDR
CDR
TMUX-D
JTAG
A
STSPP
D
STS
XC
D
MCDR
B
C
48
Mate Interconnect
(x12)
B
D
C
Partitions (A, B, C, and D)
are totally separate and can-
not be interconnected inter-
nally. For example, a DS1
out of a VTMPR from parti-
tion A cannot be sent to the
MRXC of partition B.
DS1/E1 DJA
x28/x21 (x12)
A
C
B
D
24
4
TOAC
24
DS3/E3 DJA
x6 (x4)
A
C
B
D
Power & GND
pins not shown
Clock/Sync 6
A B C D
D
MPU
64
Miscellaneous
6
JTAG IF
57
MPU IF
CS
A,B,C,D
DS1XCLK,
E1XCLK
2
DS3XCLK,
E3XCLK
02/07/05
POAC
Figure 1-1.
Hypermapper
Block Diagram and High-Level Interface Definition
TMXF33625
Hypermapper
622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0
Hardware Design Guide, Revision 6
April 5, 2005
Table of Contents
Contents
Page
1 Introduction ........................................................................................................................................................................1
2 Pin Information ...................................................................................................................................................................6
2.1 Ball Diagram .............................................................................................................................................................6
2.2 Pin Assignments .......................................................................................................................................................7
2.3 Pin Matrix ................................................................................................................................................................20
2.4 Pin Types ................................................................................................................................................................24
2.5 Pin Definitions .........................................................................................................................................................25
3 Operating Conditions and Reliability ................................................................................................................................45
3.1 Absolute Maximum Ratings ....................................................................................................................................45
3.2 Recommended Operating Conditions .....................................................................................................................45
3.3 Handling Precautions ..............................................................................................................................................45
3.4 Thermal Parameters (Definitions and Values) ........................................................................................................46
3.5 Reliability .................................................................................................................................................................47
3.6 Recommended Powerup Sequence .......................................................................................................................47
3.7 Power Consumption ................................................................................................................................................48
4 Electrical Characteristics .................................................................................................................................................49
4.1 LVCMOS Interface Characteristics .........................................................................................................................49
4.2 LVDS Interface Characteristics ...............................................................................................................................51
5 Timing ..............................................................................................................................................................................52
5.1 TMUX High-Speed Interface Timing .......................................................................................................................52
5.2 THSSYNC Characteristics ......................................................................................................................................53
5.3 STS-3/STM-1 Mate Interconnect Timing ................................................................................................................55
5.4 TOAC, POAC, and LOPOH Timing ........................................................................................................................56
5.5 DS3/E3/STS-1 Timing .............................................................................................................................................57
5.6 NSMI Timing ...........................................................................................................................................................58
5.7 CHI Timing ..............................................................................................................................................................62
5.8 Parallel System Bus (PSB) Timing .........................................................................................................................65
6 Reference Clocks ............................................................................................................................................................66
7 Microprocessor Interface Timing .....................................................................................................................................71
7.1 Synchronous Write Mode ........................................................................................................................................71
7.2 Synchronous Read Mode .......................................................................................................................................73
7.3 Asynchronous Write Mode ......................................................................................................................................74
7.4 Asynchronous Read Mode ......................................................................................................................................76
7.5 Accessing the Same Register Sequentially Across Multiple Partitions ...................................................................77
8 Other Timing ....................................................................................................................................................................78
9 Hardware Design File References ...................................................................................................................................78
10 1152-Pin PBGA6 Diagrams ............................................................................................................................................79
11 Ordering Information ......................................................................................................................................................80
12 Glossary .........................................................................................................................................................................81
13 Change History ...............................................................................................................................................................82
13.1 Navigating Through an Adobe Acrobat Document .................................................................................................82
14 Appendix ........................................................................................................................................................................83
14.1 Input Capacitances ................................................................................................................................................83
2
Agere Systems Inc.
Hardware Design Guide, Revision 6
April 5, 2005
TMXF33625
Hypermapper
622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0
Table of Contents
(continued)
Tables
Page
Table 2-1. Pin Assignments....................................................................................................................................................7
Table 2-2. Pin Matrix ............................................................................................................................................................20
Table 2-3. Pin Types ............................................................................................................................................................24
Table 2-4. TMUX Blocks, High-Speed Interface I/O.............................................................................................................25
Table 2-5. TMUX Blocks, Protection Link I/O .......................................................................................................................27
Table 2-6. TMUX Blocks, Clock and Sync I/O......................................................................................................................28
Table 2-7. STS Cross-Connect (STSXC) Blocks, STS-3/STM-1 Mate Interconnect............................................................29
Table 2-8. Multirate Cross-Connect (MRXC) Blocks, TOAC Input and Output Channels ....................................................30
Table 2-9. Multirate Cross-Connect (MRXC) Blocks, POAC Input and Output Channels....................................................31
Table 2-10. DS3/E3/STS-1 Out ............................................................................................................................................32
Table 2-11. DS3/E3/STS-1 In...............................................................................................................................................33
Table 2-12. NSMI/STS-1 In ..................................................................................................................................................34
Table 2-13. NSMI/STS-1 Out ...............................................................................................................................................35
Table 2-14. TDM Concentration Highway (CHI) In...............................................................................................................36
Table 2-15. TDM Concentration Highway (CHI) Out ............................................................................................................36
Table 2-16. Framer (FRM) Blocks, CHI/Parallel System Bus (PSB) Clock and Sync ..........................................................37
Table 2-17. Reference Clocks ..............................................................................................................................................38
Table 2-18. Low-Order Path Overhead Access, Transmit Direction ....................................................................................38
Table 2-19. Low-Order Path Overhead Access, Receive Direction .....................................................................................39
Table 2-20. Clock Generator ................................................................................................................................................39
Table 2-21. Microprocessor Interface...................................................................................................................................40
Table 2-22. Boundary Scan (IEEE 1149.1) ..........................................................................................................................41
Table 2-23. General-Purpose Interface ................................................................................................................................41
Table 2-24. CDR Interface....................................................................................................................................................42
Table 2-25. Analog Power and Ground Signals ...................................................................................................................42
Table 2-26. No Connects......................................................................................................................................................43
Table 2-27. Digital Power and Ground Signals ....................................................................................................................44
Table 3-1. Absolute Maximum Ratings.................................................................................................................................45
Table 3-2. Recommended Operating Conditions .................................................................................................................45
Table 3-3. ESD Tolerance ....................................................................................................................................................45
Table 3-4. Thermal Parameter Values .................................................................................................................................46
Table 3-5. Reliability Data ....................................................................................................................................................47
Table 3-6. Moisture Sensitivity Level....................................................................................................................................47
Table 3-7. Typical Power Consumption Per Block ...............................................................................................................48
Table 4-1. LVCMOS Input Specifications 1 ..........................................................................................................................49
Table 4-2. LVCMOS Input Specifications 2 ..........................................................................................................................49
Table 4-3. LVCMOS Input Specifications 3 ..........................................................................................................................49
Table 4-4. LVCMOS Output Specifications ..........................................................................................................................50
Table 4-5. LVCMOS Bidirectional Specifications .................................................................................................................50
Table 4-6. LVDS Interface dc Characteristics ......................................................................................................................51
Table 5-1. High-Speed Interface Input Specifications ..........................................................................................................52
Table 5-2. Protection Link Input Specifications ....................................................................................................................52
Table 5-3. High-Speed Interface Output Specifications .......................................................................................................53
Table 5-4. Protection Link Output Specifications..................................................................................................................53
Table 5-5. STS-3/STM-1 Mate Interconnect Input Specifications ........................................................................................55
Table 5-6. STS-3/STM-1 Mate Interconnect Output Specifications......................................................................................55
Table 5-7. TOAC, POAC, and LOPOH Input Specifications ................................................................................................56
Table 5-8. TOAC, POAC, and LOPOH Output Specifications..............................................................................................56
Table 5-9. DS3/E3 Input Specifications................................................................................................................................57
Table 5-10. STS-1 Input Specifications ................................................................................................................................57
Table 5-11. DS3/E3/STS-1 Output Specifications................................................................................................................57
Table 5-12. NSMI Input Specifications .................................................................................................................................61
Table 5-13. NSMI Output Specifications ..............................................................................................................................61
Table 5-14. CHIRXGCLK and CHITXGCLK Timing Specifications......................................................................................62
Table 5-15. CHI Interface Timing Specifications ..................................................................................................................62
Agere Systems Inc.
3
TMXF33625
Hypermapper
622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0
Hardware Design Guide, Revision 4
April 5, 2005
Table of Contents
(continued)
Tables
Page
Table 5-16. PSB Input Specifications ...................................................................................................................................65
Table 5-17. PSB Output Specifications ................................................................................................................................65
Table 6-1. High-Speed Interface Input Clocks Specifications ..............................................................................................66
Table 6-2. Protection Link Input Clock Specifications ..........................................................................................................66
Table 6-3. DS3/E3/STS-1 Input Clocks Specifications.........................................................................................................66
Table 6-4. DS1/E1 DJA Input Clocks Specifications ............................................................................................................67
Table 6-5. DS3/E3 DJA Input Clocks Specifications ............................................................................................................67
Table 6-6. LOPOH Input Clock Specifications......................................................................................................................67
Table 6-7. Microprocessor Interface Input Clocks Specifications.........................................................................................67
Table 6-8. Framer PLL Input Clocks Specifications .............................................................................................................67
Table 6-9. CHI Input Clocks Specifications ..........................................................................................................................68
Table 6-10. PSB Input Clocks Specifications .......................................................................................................................68
Table 6-11. High-Speed Interface Output Clocks Specifications..........................................................................................68
Table 6-12. Protection Link Output Clocks Specifications....................................................................................................68
Table 6-13. Line Timing Interface Output Clocks Specifications ..........................................................................................68
Table 6-14. TOAC Output Clocks Specifications..................................................................................................................69
Table 6-15. POAC Output Clocks Specifications .................................................................................................................69
Table 6-16. DS3/E3/STS-1 Output Clocks Specifications ....................................................................................................69
Table 6-17. LOPOH Output Clock Specifications.................................................................................................................70
Table 6-18. NSMI Output Clocks Specifications...................................................................................................................70
Table 6-19. Framer PLL Output Clocks Specifications.........................................................................................................70
Table 6-20. NSMI Input/Output Clocks Specifications..........................................................................................................70
Table 7-1. Microprocessor Interface Synchronous Write Cycle Specifications ....................................................................72
Table 7-2. Microprocessor Interface Synchronous Read Cycle Specifications ....................................................................73
Table 7-3. Microprocessor Interface Asynchronous Write Cycle Specifications ..................................................................75
Table 7-4. Microprocessor Interface Asynchronous Read Cycle Specifications ..................................................................77
Table 8-1. General-Purpose Inputs Specifications ...............................................................................................................78
Table 8-2. Miscellaneous Output Specifications...................................................................................................................78
Table 8-3. General-Purpose Output Specifications ..............................................................................................................78
Table 11-1. Ordering Information .........................................................................................................................................80
Table 13-1. Document Changes...........................................................................................................................................82
Table 14-1. Input Capacitances for Specific LVCMOS Input Pins (Specification 1)............................................................83
Table 14-2. Input Capacitances for Specific LVCMOS Input Pins (Specification 2)............................................................83
Table 14-3. Input Capacitances for Specific LVCMOS Input Pins (Specification 3)............................................................83
4
Agere Systems Inc.
Hardware Design Guide, Revision 6
April 5, 2005
TMXF33625
Hypermapper
622/155 Mbits/s SONET/SDH x DS3/E3/DS0/E0
Table of Contents
(continued)
Figures
Page
Figure 1-1. Hypermapper Block Diagram and High-Level Interface Definition.......................................................................1
Figure 2-1. Hypermapper Pin-Package Diagram (Top View) .................................................................................................6
Figure 5-1. TMUX LVDS Signal Rise/Fall Timing.................................................................................................................52
Figure 5-2. TMUX LVDS Clock and Data Timing .................................................................................................................52
Figure 5-3. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 1)................................................................................53
Figure 5-4. THSSYNC Timing Diagram (MPU_MASTER_SLAVE = 0)................................................................................53
Figure 5-5. THSSYNC Timing Diagram for Synchronized VTs ............................................................................................54
Figure 5-6. Relationship Between THSSYNC and THSD ....................................................................................................54
Figure 5-7. STS-3/STM-1 Mate Rise/Fall Timing .................................................................................................................55
Figure 5-8. STS-3/STM-1 Mate Clock and Data Timing.......................................................................................................55
Figure 5-9. TOAC, POAC Timing .........................................................................................................................................56
Figure 5-10. LOPOH Timing.................................................................................................................................................56
Figure 5-11. DS3/E3 Interface Diagram in M13/E13 Block ..................................................................................................57
Figure 5-12. NSMI Clock and Data Timing for the STS-1 Mode ..........................................................................................58
Figure 5-13. NSMI Clock and Data Diagram for SPEMPR NSMI Mode...............................................................................58
Figure 5-14. NSMI Clock and Data Diagram for M13 NSMI Mode (NSMI <---> M13 <---> DS3 External I/O).....................59
Figure 5-15. NSMI Clock and Data Diagram for E13 NSMI Mode 1 (NSMI <---> E13 <---> E3 External I/O)......................59
Figure 5-16. NSMI Clock and Data Diagram for E13 NSMI Mode 2 (NSMI <--> E13 <--> SPEMPR <--> STM-N) .............60
Figure 5-17. NSMI Clock and Data Diagram for Framer (FRM) NSMI Mode .......................................................................61
Figure 5-18. CHI Clock Timing .............................................................................................................................................62
Figure 5-19. CHI Bus Timing ................................................................................................................................................62
Figure 5-20. Typical Receive CHI Timing (Non-CMS Mode—FRM_CMS = 0) ....................................................................63
Figure 5-21. Transmit CHI Timing (Non-CMS Mode—FRM_CMS = 0)................................................................................63
Figure 5-22. Typical Receive CHI Timing (CMS Mode—FRM_CMS = 1) ............................................................................64
Figure 5-23. Transmit CHI Timing (CMS Mode—FRM_CMS = 1) .......................................................................................64
Figure 5-24. PSB Clock and Data Timing.............................................................................................................................65
Figure 7-1. Microprocessor Interface Synchronous Write Cycle (MPMODE = 1).................................................................71
Figure 7-2. Microprocessor Interface Synchronous Read Cycle (MPMODE = 1) ................................................................73
Figure 7-3. Microprocessor Interface Asynchronous Write Cycle (MPMODE = 0)...............................................................74
Figure 7-4. Microprocessor Interface Asynchronous Read Cycle (MPMODE = 0)...............................................................76
Figure 10-1. 1152-Pin PBGA6 Physical Dimensions............................................................................................................79
Agere Systems Inc.
5
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