E2/E3F Device
8-, 34 Mbit/s Framer
TXC-03701
DATA SHEET
FEATURES
• Framer for CCITT Recommendations:
- G.742 (8448 kbit/s)
- G.745 (8448 kbit/s)
- G.751 (34368 kbit/s)
- G.753 (34368 kbit/s)
• Line side interface:
- Rail or NRZ
• HDB3 codec for rail I/O
• Terminal side interface:
- Nibble-parallel
- Bit-serial
• Transmit reference generator for serial I/O
• Microprocessor or control leads
• Service bit I/O port
DESCRIPTION
The E2/E3 Framer (E2/E3F) is a CMOS VLSI device
that provides the functions needed to frame a wideband
payload to one of four CCITT Recommendations:
G.742, G.745, G.751, or G.753. The E2/E3F interfaces
to line circuitry with either rail or NRZ signals. On the
terminal side, the interface can be either nibble-parallel
or bit-serial. The nibble interface clocks are gapped for
the service bit, framing and BIP-4, if selected, times. For
the serial interface, a transmit reference generator is
provided.
The E2/E3F can be operated with or without a micropro-
cessor. When interfaced with a microprocessor, the E2/
E3F provides an 8-byte memory map for control, perfor-
mance counters and alarm status. The E2/E3F provides
a transmit and receive interface port for accessing the
overhead bits from each of the four recommendations.
The overhead bits can also be accessed by the micro-
processor via the memory map.
APPLICATIONS
• Line terminals
• Wideband data or video transport
• Test equipment
• Multiplexer systems
LINE
SIDE
+5V
TERMINAL
SIDE
NRZ
or
Rail
I/O
E2/E3F
8-, 34- Mbit/s
Framer
Receive
bit-serial/nibble-parallel
Transmit reference
generator
Transmit
bit-serial/nibble-parallel
Control
Microprocessor Service bits
Alarms leads
I/O
bus
Patents Pending
Copyright
©
1993 TranSwitch Corporation
TXC and TranSwitch are registered trademarks of TranSwitch Corporation
Document Number:
TXC-03701-MB
Ed. 4, June 1993
TranSwitch Corporation
•
8 Progress Drive
•
Shelton, CT 06484
•
USA
•
Tel: 203-929-8810
•
Fax: 203-926-9453
E2/E3F
BLOCK DIAGRAM
RDL
RCKL
RP/RDL
RN
RCK/RCKL
CV
RAIS
RLOC
BIP-4E
RLOF
ROD
ROC
ROF
FE
NRZ LINE
BIP-4
M0
M1
MICRO
SER
DAIS
TLBK
PLBK
TAIS
LPT
TLOC
FORCEFE
TOD
TOC
TOF
RESET
TP/TDL
TP/TCKL
TN
Data
Line
Decoder
Clock
Framer
Data
Clock
Frame
Data
Interpreter
Clock
Frame
Output
SERIAL
RSD
TDOUT
TCG
TFOUT
RSC
RSF
RCG
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
SEL
ALE
RD
WR
RDY
PARALLEL
RNIB3
RNIB2
RNIB1
RNIB0
RNC
RNF
N.C.
Micro-
processor
I/O
Control
Transmit
Reference
Generator
XSF
N.C.
TCIN
XSD
XCK
N.C.
TCOUT
XNIB3
XNIB2
XNIB1
XNIB0
XCK
XNF
XNC
TCKL
TDL
Line
Encoder
Data
Clock
G.7XX
Send
Input
Clock
Data
Framing
Line Side
Figure 1. E2/E3F Block Diagram
Terminal Side
BLOCK DIAGRAM DESCRIPTION
The block diagram for the E2/E3F is shown in Figure 1. The E2/E3F receives a line side NRZ data signal
(RDL) and clock signal (RCKL), or a positive (RP) and negative (RN) rail signal and clock signal (RCK), from a
TranSwitch MRT, or from another line interface circuit. The selection of the line interface, rail or NRZ, is con-
trolled by the external lead labeled NRZ LINE. Indications of HDB3 coding violation errors are detected in the
Line Decoder Block and are provided on an external signal lead (CV) as pulses. Coding violation errors are
also counted in an 8-bit saturating counter accessed by the microprocessor through the memory map. A cod-
ing violation is not part of the standard HDB3 zero-substitution code, and occurs because of noise or other
impairments on the line.
The selection of one of the four G.7XX framing formats (G.742, G.745, G.751, and G.753) which are supported
by the E2/E3F is determined by external control leads (M1 and M0), or states written into the memory map by
the microprocessor. The Framer Block performs frame alignment and alarm detection. The E2/E3F Framer
Block detects Loss of Frame (RLOF), Loss of Clock (RLOC), and performs AIS detection (RAIS) and BIP-4 (Bit
Interleaved Parity-4) detection (BIP-4E) when this feature is enabled in the nibble-parallel mode. Loss of clock
is detected whether the clock is stuck high or low. A framing error (FE) output is also provided to indicate when
any of the framing bits in the G. 7XX frame are in error. Loss of the receive clock or framing normally causes
AIS to be inserted into the terminal side data stream. However, for some applications, receive data is required
on the terminal side regardless of frame alignment. The disable AIS (DAIS) control lead permits the E2/E3F to
provide receive data in the presence of loss of frame. The external alarm indications (latched and unlatched
states) are provided in the memory map, and unlatched alarm indications are provided at signal leads.
-2-
E2/E3F
The service bits are defined as bits 11 and 12 for G.742 and G.751, as listed in Table 1. The service bits for
G.745 and G.753 are defined as bits 5 through 8 in sets II and III. The receive service bit interface consists of
the following signals: data output signal (ROD), clock output signal (ROC), and framing pulse (ROF). The clock
signal (ROC) is gapped and is provided for clocking out the service bits. The service bit states are also written
into E2/E3F memory locations by the Interpreter Block, which can be read by the microprocessor if the signal-
ing rate is low.
Table 1. G.7XX Summary
Recommendation
G.742
G.745
G.751
G.753
Service Bits
11,12
5-8 Set II
5-8 Set III
11,12
5-8 Set II
5-8 Set III
Bit Locations
11,12
269-272
533-536
11,12
721-724
1437-1440
No. of Bits in
Frame
848
1056
1536
2148
Bit Rate
(kbit/s)
8448
8448
34368
34368
The E2/E3F terminal side Output Block provides either a bit-serial or a nibble-parallel interface. The interface
is selected by an external control lead (SER) or by setting a control bit in the memory map. The bit-serial inter-
face consists of the following signals: a data output signal (RSD), a clock output signal (RSC), a receive clock
gapped output signal (RCG), and a framing pulse (RSF). The receive clock gapped signal (RCG) is active low
during the framing and service bit times. The nibble-parallel interface consists of the following signals: a data
output signal having a nibble format (RNIB3 through RNIB0), a clock output signal (RNC), and a framing pulse
(RNF). Signal leads are shared for the two interfaces (RSD and RNIB3, RSC and RNC, RSF and RNF) and
with the transmit reference generator, which is used in the serial mode only. The RNIB3 bit corresponds to the
first bit received in a four bit-serial bit stream segment. In the nibble mode, the framing pattern, service bits and
BIP-4 nibble are not provided at the interface. The receive nibble clock (RNC) is gapped during framing pat-
tern, service bit and BIP-4 times.
The transmitter operates independently of the receiver, unless the loop timing feature is selected. When the
loop timing feature is selected, the receive clock becomes the transmitted clock. In the transmit direction, the
terminal side bit-serial interface consists of the following signals: a data input signal (XSD), a clock input signal
(XCK), and a framing pulse (XSF). The nibble-parallel interface consists of the following signals: a data input
signal having a nibble format (XNIB3 - XNIB0), a clock input signal (XCK), a framing output pulse (XNF), and a
nibble output clock signal (XNC). The leads are shared between the two interfaces and with the E2/E3F trans-
mit reference generator in order to minimize the pin count. The XNIB3 bit corresponds to the first bit transmit-
ted in a four bit-serial bit stream segment. The transmit nibble clock (XNC) is stretched to accommodate the
framing pattern, service bit and BIP-4 times. The E2/E3F also detects loss of clock (TLOC) whether the input
clock is stuck high or low.
The transmitter has control leads for BIP-4 generation (BIP-4) and inserting AIS (TAIS). When the E2/E3F is
operating with a microprocessor, the BIP-4 and AIS functions are controlled by the microprocessor. When the
BIP-4 option is selected, the BIP-4 is transmitted as the last nibble in the frame format, as shown in Figure 2.
-3-
E2/E3F
Bit 1
11100110
DATA
G.745 Frame
SET II
SERVICE
BITS
DATA
SET III
SERVICE
BITS
DATA
1053
BIP-4
1056
When BIP-4 feature
is selected
Figure 2. G.745 BIP-4 Location
The transmitted service bits are inserted into the frame format from either an external interface or from memory
map locations. The transmit service bit interface consists of the following signals: a data in signal (TOD), a
clock output signal (TOC), and a framing pulse (TOF).
To facilitate transmit side multiplexing while operating in the bit-serial mode, the E2/E3F provides a transmit
frame reference generator. The transmit frame reference generator accepts an external 8.448 or 34.368 MHz
clock signal (TCIN) and produces a clock out signal (TCOUT), a framing pulse (TFOUT), a clock gap signal
(TCG), and a data signal (TDOUT). The data signal consists of G.7XX framing bits and zeros elsewhere. The
purpose of the transmit reference signals is to fix the transmit time-base for the terminal payload multiplexer
circuitry.
The selection of the transmit line interface, rail or NRZ, is controlled by the state present on the NRZ line con-
trol lead, which also controls the receive interface selection. When the internal HDB3 Encoder Block is
bypassed, the transmit line interface consists of a data signal (TDL) and a clock signal (TCKL). When the
HDB3 encoder is enabled, the transmit line interface consists of positive (TP) and negative (TN) rail signals
and a clock signal (RCK).
A high placed on the microprocessor control lead (MICRO) selects the microprocessor interface. All the exter-
nal control leads, except the loop timing (LPT), receive AIS disable, and the line interface control leads are dis-
abled when the microprocessor interface is selected. The E2/E3F provides pull-up resistors for the active low
control leads.
The microprocessor interface consists of eight bidirectional data and address leads (AD7 - AD0), along with
other microprocessor control leads, including a ready (RDY) signal.
-4-
E2/E3F
PIN DIAGRAM
RNIB2/TDOUT
RNIB0/TFOUT
RNIB1/TCG
RNIB3/RSD
RCK/RCKL
RNC/RSC
RNF/RSF
62
RP/RDL
RLOC
RLOF
RAIS
ROD
68
GND
VDD
RN
CV
67
66
65
64
ROC
ROF
FE
NRZLINE
BIP-4
M0
M1
VDD
GND
MICRO
SER
TLBK
PLBK
TAIS
LPT
TLOC
FORCEFE
63
9
8
7
6
5
4
3
2
1
RCG
60
59
58
57
56
BIP-4E
XNC/TCOUT
XNF
XCK
XNIB0/XSD
XNIB1/TCIN
XNIB2
XNIB3/XSF
GND
VDD
N.C.
DAIS
RDY
WR
RD
ALE
SEL
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
AD1
26
E2/E3F
Pin Diagram
(Top View)
55
54
53
52
51
50
49
48
47
46
45
43
AD0
TCK/TCKL
TOD
TOC
TOF
TP/TDL
RESET
GND
VDD
AD7
AD6
AD5
AD4
AD3
Figure 3. E2/E3F Pin Diagram
PIN DESCRIPTIONS
Power Supply and Ground:
Symbol
VDD
GND
N.C.
Pin No.
1,17,35,51
18,34,52,68
50
I/O/P*
P
P
Type
Name/Function
VDD:
5-volt supply voltage, +/- 5%
Ground.
No Connection.
*Note: I = Input; O = Output; P = Power
-5-
AD2
TN
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