CXA2025AS
Y/C/RGB/Sync/Deflection for Color TV
Description
The CXA2025AS is a bipolar IC which integrates
the luminance signal processing, chroma signal
processing, RGB signal processing, and sync and
deflection signal processing functions for NTSC
system color TVs onto a single chip.
The following functions have been added to the
same function IC, CXA2025S.
1) Vertical sync pull-in speed switching function
2) YUV SW Y signal switching function
Features
•
I
2
C bus compatible
•
Sync signal processing uses a countdown system
with non-adjusting H/V oscillator frequencies
•
Built-in deflection compensation circuit capable of
supporting various wide modes
•
Non-adjusting Y/C block filter
•
Built-in AKB
•
Video signal I/Os: Y/C separation input, Y/color
difference input, analog RGB input and RGB
output
•
YUV SW Y signal switching function allows picture
quality adjustment for the Y signal in the same
manner as for the normal Y signal even when
Y/color difference input is selected
Applications
Color TVs (4:3, 16:9)
Structure
Bipolar silicon monolithic IC
SAWOSC
VAGCSH
EWDRIVE
48 pin SDIP (Plastic)
Absolute Maximum Ratings
(Ta = 25°C, SGND, JGND = 0V)
•
Supply voltage
SV
CC
, JV
CC
–0.3 to +12 V
•
Operating temperature
Topr
–20 to +75 °C
•
Storage temperature
Tstg
–65 to +150 °C
•
Allowable power dissipation
P
D
1.5
W
•
Voltages at each pin –0.3 to SV
CC
, JV
CC
+ 0.3 V
Operating Conditions
Supply voltage
SV
CC
JV
CC
9.0 ± 0.5
9.0 ± 0.5
V
V
VDRIVE+ /VPROT
VDRIVE– /VPROT
AFCFIL
HDRIVE
VTIM (SCP)
Pin Configuration
VSFIL
CERA
JGND
HSIN
VSIN
L2FIL
IREF
BGP
NC
NC
VM
ABLIN/VCOMP
26
23
AFCPIN/HOFF
ABLFIL
JV
CC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
24
BLHOLD
SGND
EYIN
ROUT
XTAL
BSH
SCL
GIN
YIN
ERYIN
APCFIL
EBYIN
YUV SW
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
GOUT
E96413-ST
BOUT
YM
SV
CC
GSH
SDA
CIN
BIN
YS
RSH
RIN
IKIN
Block Diagram
L2FIL
AFCFIL
ABLIN
/VCOMP
ABLFIL
JGND
CERA
JV
CC
SAWOSC
VAGCSH
EWDRIVE
VDRIVE+
VTIM
SDA
SCL
IREF
HSIN
NC
NC
BGP
VDRIVE–
/VPROT
VSIN
VSFIL
AFCPIN
/HOFF
8
34
29
25
7
46
48 47
39
30
28
26
27
36
33
31
38
41
43
42
44
40
32
37
35
I
2
C BUS
DECODER
32f
H
VCO
H DRIVE
IREF
HDRIVE
VSYNC
SEP.
HSYNC
SEP.
PHASE
DETECTOR
H PHASE
DETECTOR
V SAW
OSC/AGC
V PARA
GEN.
V SAW
GEN.
D/A
V COUNT DOWN
1/32
DIVIDER
WIDE
MODE
H PHASE
SHIFTER
V ZOOMING
TIMING PULSE GEN.
ABL
VM
YM
YS
YIN
CIN
RIN
GIN
BIN
XTAL
SV
CC
EYIN
RSH
GSH
BSH
BOUT
APCFIL
BLHOLD
YUVSW
ERYIN
EBYIN
SGND
GOUT
ROUT
–2–
AXIS
Y/C MIX
KILLER
DETECTOR
COLOR
CHROMA
DEMOD.
YUV SW
YM ATT.
CHROMA
APC
HUE
CHROMA
VCO
YUV
CLAMP
AMP
2
1
6
9
10
11
12
13
14
15
Y DELAY
SHARPNESS
CLAMP
DC-TRAN
D-PIC
PICTURE
D-COL
GAMMA
CLAMP
BRIGHT
DRIVE
YS SW
REF-P SW
AKB/CUTOFF/IK
C-TRAP
TOT
SUBCONT
VM AMP
BLANKING BUFFER
RGB CLAMP
ACC AMP
4
45
3
5
16
17
18
19
21
23
24
22
20
IKIN
CXA2025AS
CXA2025AS
Pin Description
Pin
No.
Symbol
Equivalent circuit
Description
SV
CC
1
XTAL
350
1
200µ
Connect a 3.579545MHz crystal oscillator.
SV
CC
1.2k
2
APCFIL
1.2k
2
CR connection for the chroma APC lag-lead
filter.
50µ
50µ
SV
CC
9µ
20k
3
BLHOLD
3
4k
20k
1.2k
25µ
Capacitor connection for black peak hold of the
dynamic picture (black expansion).
SV
CC
1.2k
4
YIN
4
100µ
Y signal input.
Input a 2Vp-p (including sync, 100% white) Y
signal via a capacitor. The pedestal level of the
input signal is clamped to 4.2V.
SV
CC
10p
5
CIN
5
30k
35µ
Chroma signal input.
Provide a bias of about V
CC
/2 and input a C
signal (including sync, 100% white, 2Vp-p CV
signal) with a 570mVp-p burst level.
6
SV
CC
JV
CC
4k
50µ
Power supply for the video block.
7
SCL
7
I
2
C bus protocol SCL (Serial Clock) input.
VILMAX = 1.5V
VIHMIN = 3.5V
10k
–3–
CXA2025AS
Pin
No.
Symbol
Equivalent circuit
JV
CC
50µ
Description
8
SDA
8
I
2
C bus protocol SDA (Serial Data) I/O.
VILMAX = 1.5V
VIHMIN = 3.5V
VOLMAX = 0.4V
SV
CC
100µ
9
YUV SW
9
147
40k
Switch control for the external YUV signal input.
When YUV SW is high, the external YUV signal
is selected; when YUV SW is low, the Y/C block
signal is selected. However, when the EY-SW
register is 1, the YIN (Pin 4) input is selected for
the Y signal even if YUV SW is high.
VILMAX = 0.4V
VIHMIN = 1.0V
VIHMAX = 3.0V
10
EYIN
External Y signal input.
Input a 0.7Vp-p (100 IRE) Y signal via a
capacitor. The signal is clamped to 6.5V at the
burst timing of the signal input to the sync input
pin (Pin 44).
SV
CC
2k
1k
11
ERYIN
10
11
12
40k
External R-Y signal input.
Input a 0.78Vp-p (color difference signal
obtained by detecting a 100 IRE, 0.7Vp-p,
100% color bar chroma signal at the orthogonal
axis) + (R-Y) signal via a capacitor. The signal
is clamped to 6.2V at the burst timing of the
signal input to the sync input pin (Pin 44).
12
EBYIN
External B-Y signal input.
Input a 1.0Vp-p (color difference signal obtained
by detecting a 100 IRE, 0.7Vp-p, 100% color
bar chroma signal at the orthogonal axis) + (B-
Y) signal via a capacitor. The signal is clamped
to 6.2V at the burst timing of the signal input to
the sync input pin (Pin 44).
GND for the video block.
SV
CC
100µ
13
SGND
14
YM
147
14
40k
YM switch control input.
When YM is high, the Y/C block signal is
attennated by 6dB.
VILMAX = 0.4V
VIHMIN = 1.0V
VIHMAX = 3.0V
–4–
CXA2025AS
Pin
No.
Symbol
Equivalent circuit
SV
CC
100µ
Description
YS switch control input.
When YS is high, the RGB block signal is
selected; when YS is low, the Y/C block is
selected.
VILMAX = 0.4V
VIHMIN = 1.0V
VIHMAX = 3.0V
15
YS
147
15
40k
SV
CC
200
16
17
18
RIN
GIN
BIN
16
17
18
30k
Analog R, G and B signal input.
Input a 0.7Vp-p (no sync, 100 IRE) signal via a
capacitor. The signal is clamped to 5.1V at the
burst timing of the signal input to the sync input
pin (Pin 44).
SV
CC
1k
19
21
23
RSH
GSH
BSH
19
21
23
50µ
Sample-and-hold for R, G and B AKB.
Connect to GND via a capacitor. When not using
AKB (manual cut-off mode), R, G and B cut-off
voltage can be controlled by applying a control
voltage to each pin. The control voltage is 4.2 ±
2V.
SV
CC
200
20
22
24
ROUT
GOUT
BOUT
12k
20
1100µ
R, G and B signal output.
2.4Vp-p is output during 100% white input.
SV
CC
1k
25
IKIN
25
50µ
Input the signal converted from the CRT beam
current (cathode current IK) to a voltage via a
capacitor. The V blanking part is clamped to 2.7V at
the V retrace timing.
The input for this pin is the reference pulse return,
and the loop operates so that the Rch is 1Vp-p and
the G and Bch are 0.83Vp-p. The G and Bch can be
varied by ±0.5V by the bus CUTOFF control. When
not using AKB, this pin should not be connected.
ABL control signal input and VSAW high voltage
fluctuation compensation signal input.
High voltage compensation has linear control
characteristics for the pin voltage range of about
3V to 1V.
ABL does not operate when the pin voltage is 9
[V], and operates with increasing strength as the
voltage becomes lower than 9 [V].
SV
CC
26
ABLIN
/VCOMP
147
26
–5–
综合技术交流
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
