HB52RF649E1U-75B
512 MB Registered SDRAM DIMM
64-Mword
×
72-bit, 133 MHz Memory Bus, 1-Bank Module
(18 pcs of 64 M
×
4 Components)
PC133 SDRAM
ADE-203-1193A (Z)
Preliminary
Rev. 0.1
Oct. 6, 2000
Description
The HB52RF649E1U belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been
developed as an optimized main memory solution for 8-byte processor applications. The HB52RF649E1U is
a 64M
×
72
×
1-bank Synchronous Dynamic RAM Registered Module, mounted 18 pieces of 256-Mbit
SDRAM (HM5225405BTB) sealed in TCP package, 1 piece of PLL clock driver, 2 pieces of register driver
and 1 piece of serial EEPROM (2-kbit) for Presence Detect (PD). An outline of the HB52RF649E1U is 168-
pin socket type package (dual lead out). Therefore, the HB52RF649E1U makes high density mounting
possible without surface mount technology. The HB52RF649E1U provides common data inputs and outputs.
Decoupling capacitors are mounted beside each TCP on the module board.
Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would
be electrical defects.
Features
•
Fully compatible with : JEDEC standard outline 8-byte DIMM
•
168-pin socket type package (dual lead out)
Outline: 133.35 mm (Length)
×
30.48 mm (Height)
×
4.80 mm (Thickness)
Lead pitch: 1.27 mm
•
3.3 V power supply
•
Clock frequency: 133 MHz (max)
•
LVTTL interface
•
Data bus width:
×
72 ECC
•
Single pulsed
RAS
Preliminary: The Specifications of this device are subject to change without notice. Please contact to your nearest
Hitachi’s sales Dept. regarding specifications.
HB52RF649E1U-75B
•
•
•
•
4 Banks can operates simultaneously and independently
Burst read/write operation and burst read/single write operation capability
Programmable burst length: 1/2/4/8
2 variations of burst sequence
Sequential
Interleave
Programmable
CE
latency
: 4 (133 MHz)
: 3 (100 MHz)
Byte control by DQMB
Refresh cycles: 8192 refresh cycles/64 ms
2 variations of refresh
Auto refresh
Self refresh
•
•
•
•
Ordering Information
Type No.
HB52RF649E1U-75B*
1
Note:
Frequency
133 MHz
CE
latency
4
Package
Contact pad
168-pin dual lead out socket type Gold
1. 100 MHz operation at
CE
latency = 3.
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
84 pin
85 pin 94 pin 95 pin 124 pin 125 pin
168 pin
2
HB52RF649E1U-75B
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
Pin name
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
V
CC
W
DQMB0
DQMB1
S0
NC
V
SS
A0
A2
A4
Pin No.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
Pin name
V
SS
NC
S2
DQMB2
DQMB3
NC
V
CC
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
CC
DQ20
NC
NC
NC
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
Pin No.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
Pin name
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
CC
DQ46
DQ47
CB4
CB5
V
SS
NC
NC
V
CC
CE
DQMB4
DQMB5
NC
RE
V
SS
A1
A3
A5
Pin No.
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
Pin name
V
SS
CKE0
NC
DQMB6
DQMB7
NC
V
CC
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
CC
DQ52
NC
NC
REGE
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
3
HB52RF649E1U-75B
Pin No.
36
37
38
39
40
41
42
Pin name
A6
A8
A10 (AP)
BA1
V
CC
V
CC
CK0
Pin No.
78
79
80
81
82
83
84
Pin name
V
SS
CK2
NC
WP
SDA
SCL
V
CC
Pin No.
120
121
122
123
124
125
126
Pin name
A7
A9
BA0
A11
V
CC
CK1
A12
Pin No.
162
163
164
165
166
167
168
Pin name
V
SS
CK3
NC
SA0
SA1
SA2
V
CC
Pin Description
Pin name
A0 to A12
Function
Address input
Row address A0 to A12
Column address A0 to A9, A11
BA0/BA1
DQ0 to DQ63
CB0 to CB7
S0, S2
RE
CE
W
DQMB0 to DQMB7
CK0 to CK3
CKE0
WP
REGE*
1
SDA
SCL
SA0 to SA2
V
CC
V
SS
NC
Note:
Bank select address
Data input/output
Check bit (Data input/output)
Chip select input
Row enable (RAS) input
Column enable (CAS) input
Write enable input
Byte data mask
Clock input
Clock enable input
Write protect for serial PD
Register enable
Data input/output for serial PD
Clock input for serial PD
Serial address input
Primary positive power supply
Ground
No connection
1. REGE is the Register Enable pin which permits the DIMM to operate in “buffered” mode and
“registered” mode. To conform to this specification, mother boards must pull this pin to high state
(“registerd” mode).
4
HB52RF649E1U-75B
Serial PD Matrix*
1
Byte No. Function described
0
1
2
3
4
5
6
7
8
9
Number of bytes used by
module manufacturer
Total SPD memory size
Memory type
Number of row addresses bits
Number of column addresses
bits
Number of banks
Module data width
Module data width (continued)
Module interface signal levels
SDRAM cycle time
(highest
CE
latency)
7.5 ns
SDRAM access from Clock
(highest
CE
latency)
5.4 ns
Module configuration type
Refresh rate/type
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
0
1
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
80
08
04
0D
0B
01
48
00
01
75
128
256 byte
SDRAM
13
11
1
72 bit
0 (+)
LVTTL
CL = 3
10
0
1
0
1
0
1
0
0
54
*
5
11
12
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
02
82
ECC
Normal
(7.8125
µs)
Self refresh
64M
×
4
×
4
1 CLK
13
14
15
SDRAM width
Error checking SDRAM width
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
04
04
01
SDRAM device attributes:
0
minimum clock delay for back-to-
back random column addresses
SDRAM device attributes:
Burst lengths supported
SDRAM device attributes:
number of banks on SDRAM
device
SDRAM device attributes:
CE
latency
SDRAM device attributes:
S
latency
SDRAM device attributes:
W
latency
SDRAM device attributes
0
0
16
17
0
0
0
0
0
0
1
0
1
1
1
0
1
0
0F
04
1, 2, 4, 8
4
18
19
20
21
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
1
0
1
1
0
06
01
01
16
2/3
0
0
Registered
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
